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int main()
{// setting up the AIC24 handle
AIC24_InitDefaults(⩓hAIC24, 4, 64, r_data1, r_data2, w_data1, w_data2, process);hAIC24.Regs[0].creg6.reg6a.control_bit.mici = 0;hAIC24.Regs[0].creg6.reg6a.control_bit.inp1 = 0;hAIC24.Regs[0].creg6.reg6a.control_bit.inp2 = 0;hAIC24.Regs[0].creg6.reg6a.control_bit.inp3 = 1;hAIC24.Regs[0].creg6.reg6a.control_bit.inp4 = 0;// Starting the AIC24
AIC24_Start(⩓hAIC24);}
Each entry corresponds to a bit that determines whether it should be connected or not to the channel input Other entries were reset ('0'), as they should not be connected to the channel's input. . The names of the fields correlate to the table.
A similar procedure applies for the output channel:
hAIC24.Regs[0].creg6.reg6b.control_bit.outp1 = 0;hAIC24.Regs[0].creg6.reg6b.control_bit.outp2 = 1;hAIC24.Regs[0].creg6.reg6b.control_bit.outp3 = 0;
In the case above, output of channel 0 is connected to OUTP2 (i.e. J1).
A single channel can be connected to a number of outputs. It is not recommended to connect two CODEC channels to a single output.
The default channel configuration is:
Even Channels (i.e. 0,2,…) Input: MICI
Even Channels (i.e. 0,2,…) Output: OUTP1
Odd Channels (i.e. 1,3,…) Input: INP1
Odd Channels (i.e. 1,3,…) Output: OUTP2
| Jumper | State |
| W1: | Closed |
| W2: | 2-3 |
| W3: | 1-2 |
| W4: | 1-2 |
| W5: | Closed |
| P1.13-P1.14: | Closed |
| P1.9-P1.10: | Closed |
| P1.11-P1.12: | Closed |
| Jumper | State |
| W1: | 1-2 |
| W2: | 2-3 |
| Register | Value | Remarks |
| opt | EDMA_OPT_PRI_LOW | Low Priority (Allows other DMAs first) |
| EDMA_OPT_ESIZE_16BIT | 16 bits elements | |
| EDMA_OPT_2DS_NO | Source not using 2D option | |
| EDMA_OPT_SUM_NONE | Source Address is fixed (The MCBSP rcv register) | |
| EDMA_OPT_2DD_NO | Destination not using 2D option | |
| EDMA_OPT_DUM_IDX | Destination address is in double index (sort) mode | |
| EDMA_OPT_TCINT_YES | Cause interrupt | |
| EDMA_OPT_TCC_OF(0) | Transfer Complete Code (given to the interrupt, set later) | |
| EDMA_OPT_LINK_YES | Use linking to another EDMA record | |
| EDMA_OPT_FS_NO | Don't use frame sync | |
| src | MCBSP_getRcvAddr(hAIC->hMcbsp) | The address of the McBSP recv register |
| cnt | EDMA_CNT_FRMCNT_OF(ChannelBufferSize – 1) | The number of frames is the size of the buffer |
| EDMA_CNT_ELECNT_OF(TotalNumChannels) | Each frame has NumChannel elements | |
| dst | EDMA_DST_OF(ReadAddr) | The address of the buffer to write to |
| idx | EDMA_IDX_FRMIDX_OF(-((ChannelBufferSize * (TotalNumChannels-1)) * 2)+2 | Negative Frame Index to move us back to the next position in the first channel after each frame |
| EDMA_IDX_ELEIDX_OF((ChannelBufferSize * 2) | Positive Element Index to move us to the next position in channel after every elemnt | |
| rld | EDMA_RLD_ELERLD_OF(TotalNumChannels) | Should be the same as Element Count |
| EDMA_RLD_LINK_OF(LinkedRecord) | The number of the next record to load (since we use double buffering the next record will point back to this one) |
| Register | Value | Remarks |
| opt | EDMA_OPT_PRI_LOW | Low Priority (Allows other DMAs first) |
| EDMA_OPT_ESIZE_16BIT | 16 bits elements | |
| EDMA_OPT_2DS_NO | Source not using 2D option | |
| EDMA_OPT_SUM_IDX | Source address is in double index (sort) | |
| EDMA_OPT_2DD_NO | Destination not using 2D option | |
| EDMA_OPT_DUM_NONE | Destination Address is fixed (The MCBSP xmt register) | |
| EDMA_OPT_TCINT_YES | Cause interrupt | |
| EDMA_OPT_TCC_OF(0) | Transfer Complete Code (given to the interrupt, set later) | |
| EDMA_OPT_LINK_YES | Use linking to another EDMA record | |
| EDMA_OPT_FS_NO | Don't use frame sync | |
| src | EDMA_SRC_OF(WriteAddr) | The address of the buffer read from |
| cnt | EDMA_CNT_FRMCNT_OF(ChannelBufferSize – 1) | Each frame has NumChannel elements |
| EDMA_CNT_ELECNT_OF(TotalNumChannels) | Each frame has NumChannel elements | |
| dst | MCBSP_getXmtAddr(hAIC->hMcbsp) | The address of the McBSP transmit register |
| idx | EDMA_IDX_FRMIDX_OF(-((ChannelBufferSize * (TotalNumChannels-1)) * 2)+2) | Negative Frame Index to move us back to the next position in the first channel after each frame |
| EDMA_IDX_ELEIDX_OF((ChannelBufferSize * 2)) | Positive Element Index to move us to the next position in channel after every elemnt | |
| rld | EDMA_RLD_ELERLD_OF(TotalNumChannels) | Should be the same as Element Count |
| EDMA_RLD_LINK_OF(LinkedRecord) | The number of the next record to load (since we use double buffering the next record will point back to this one) |
| Register | Value | Remarks |
| Serial Port Control Register (SPCR) | MCBSP_SPCR_FREE_YES | Used for emulation |
| MCBSP_SPCR_SOFT_YES | Used for emulation | |
| MCBSP_SPCR_FRST_YES | Frame sync generator is in reset (generated by master CODEC) | |
| MCBSP_SPCR_GRST_YES | Sample rate generator is in reset (generated by master CODEC) | |
| MCBSP_SPCR_XINTM_FRM | The transmit interrupt is driven by new frame sync | |
| MCBSP_SPCR_XSYNCERR_NO | No synchronization error detected | |
| MCBSP_SPCR_XRST_YES | The serial port transmitter is disabled and in reset state | |
| MCBSP_SPCR_DLB_OFF | Digital Loopback mode off | |
| MCBSP_SPCR_RJUST_RZF | Receive data right-justified and zero-fill MSBSs in DRR | |
| MCBSP_SPCR_CLKSTP_DISABLE | The Clock stop mode is disabled | |
| MCBSP_SPCR_DXENA_OFF | Disable extra delay of DX | |
| MCBSP_SPCR_RINTM_FRM | Receive interrupt on new frame synch | |
| MCBSP_SPCR_RSYNCERR_NO | No synchronization error detected | |
| MCBSP_SPCR_RRST_YES | The serial port receiver is disabled and in reset state | |
| Receive Control Register (RCR) | MCBSP_RCR_RPHASE_SINGLE | receive one phase only |
| MCBSP_RCR_RFRLEN2_OF(0) | Don't Care. Phase 2 is not used | |
| MCBSP_RCR_RWDLEN2_16BIT | Don't Care. Phase 2 is not used | |
| MCBSP_RCR_RCOMPAND_MSB | No companding, data transfer starts with MSB first | |
| MCBSP_RCR_RFIG_NO | sync error doesn't cause transfer restart | |
| MCBSP_RCR_RDATDLY_1BIT | 1 bit data delay | |
| MCBSP_RCR_RFRLEN1_OF(NumChannels-1) | Each frame contains an element for each channel | |
| MCBSP_RCR_RWDLEN1_16BIT | Each sample is 16 bit | |
| MCBSP_RCR_RWDREVRS_DISABLE | Don't Care. Only 16 bit elements are used | |
| Transmit Control Register (XCR) | MCBSP_XCR_XPHASE_SINGLE | Transmit one phase only |
| MCBSP_XCR_XFRLEN2_OF(0) | Don't Care. Phase 2 is not used | |
| MCBSP_XCR_XWDLEN2_16BIT | Don't Care. Phase 2 is not used | |
| MCBSP_XCR_XCOMPAND_MSB | No companding, data transfer starts with MSB first | |
| MCBSP_XCR_XFIG_NO | sync error doesn't cause transfer restart | |
| MCBSP_XCR_XDATDLY_1BIT | 1 bit data delay | |
| MCBSP_XCR_XFRLEN1_OF(NumChannels-1) | Each frame contains an element for each channel | |
| MCBSP_XCR_XWDLEN1_16BIT | Each sample is 16bit | |
| MCBSP_XCR_XWDREVRS_DISABLE | Does not matter, we use 16 bit elements | |
| Sample Rate Generator Register (SRGR) | 0 | Not used, clock and frame sync are generated by the master CODEC (The source code contains the flags but they are 0) |
| Pin Control Register (PCR) | MCBSP_PCR_XIOEN_SP | All pins are dedicated for MCBSP (Not GPIO) |
| MCBSP_PCR_RIOEN_SP | All pins are dedicated for MCBSP (Not GPIO) | |
| MCBSP_PCR_FSXM_EXTERNAL | Transmit frame sync is generated by the master CODEC | |
| MCBSP_PCR_FSRM_EXTERNAL | Receive frame sync is generated by the master CODEC | |
| MCBSP_PCR_CLKXM_INPUT | Transmit clock sync is generated by the master CODEC | |
| MCBSP_PCR_CLKRM_INPUT | Receive clock sync is generated by the master CODEC | |
| MCBSP_PCR_CLKSSTAT_0 | Does not matter (used in GPIO) | |
| MCBSP_PCR_DXSTAT_0 | Does not matter (used in GPIO) | |
| MCBSP_PCR_FSXP_ACTIVEHIGH | Transmit frame sync is active high for AIC24 | |
| MCBSP_PCR_FSRP_ACTIVEHIGH | Receive frame sync is active high for AIC24 | |
| MCBSP_PCR_CLKXP_RISING | Transmit data driven on rising edge | |
| MCBSP_PCR_CLKRP_FALLING | Receive data sampled on falling edge | |
| MCR | 0 | Unused |
| RCER | 0 | Unused |
| XCER | 0 | Unused |
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