9.28 Sspd_chapter 7_part 7_scaling of mos circuits_concluded.  (Page 4/4)

Thermal and Thermofluid modeling software is being accepted for simulation based development and implementation of advanced packages. High performance, air-cooled heat sinks will dominate future applications.

7.7.11.The Challenges being posed by Scaling.

7.7.11.1. High-K dielectric for Gate Insulation.

The biggest challenge is the unacceptably thin gate oxide with advanced scaling.

Table 7.7.11.1 gives the thicknesses of gate oxide with advanced Generation of MOS devices.

Table 7.7.11.1. The Gate Oxide Thickness (D nm) in advanced Generations of Devices.

We see that as we reach 90nm Generattion of Devices, the oxide layer becomes:

At 5 atomic layer thick Gate Oxide direct Quantum Mechanical tunneling is enabled leading to high Gate leakage and increased static power dissipation. The only solution was to make it physically thick but keep it electrically thin so that threshold voltage is unaffected., So we go for high K dielectric material for gate insulation.

Since Gate Capacitance has to remain constant therefore:

Therefore:

So if a high K material 5× the dielectric constant of SiO ₂ is used we will have 5× thick oxide layer that is 6.5nm thick dielectric material at the Gate which will completely cutoff the leakage and hence we normalize the statric power dissipation to nW in CMOS logic..

High K dielectrics are HfO ₂ with K=15 to 30 or HfSiO ₂ with K= 12 to 16..

7.7.11.2. Poly-Silicon Gate should be replaced by Metal as Silicon Dioxide replaced by High-K insulator.

The scaling forces SiO ₂ to be replaced by high-K insulator but it simultaneously demands Poly-Si to be replaced by Metal. As we progress with scaling Poly-Si becomes less effective as Gate. There are three reasons for this:

1. Because of Fermi-level pinning we get higher threshold voltage;
2. High-K material has high elasticity hence results in higher phonon or lattrice scattering. This results in the deterioration of channel conductivity;
3. Poly-Si has poor bonding with high-K insulator.

Therefore Poly-Si has to be replaced by Metal again as it was in the start of IC

Technology.

7.7.11.3.Strained Silicon for enhanced channel mobility.

To further solve the problem of reduced channel mobility, Uniaxial Process induced Stress could be used for enhanced mobility and hence for higher channel conductivity.

7.7.12. Concluding Remarks on Scaling.

Table 7.7.12.1. gives the typical scaling factors which have been used for the advanced Generations of the Devices.(Reference:”Device Scaling:The Treadmill that fuelled Semiconductor Industry Growth” by Pallab Chatterjee, i2 Technologies, Inc.)

Table. 7.7.12.1.Semiconductor Association Association 1992 Overall Road Map Technology Characteristics.

In addition to speed and packing density, scaled CMOS provides new opportunities in low power management. Speed can be traded off fiir reduction in power consumption.

40N. AA NiMH Battery Cells are required for FULL MOTION VIDEO PLAYER in 0.5μm technology.

1No. AA NiMH Battery Cells are required for FULL MOTION VIDEO PLAYER in 0.1μm technology.

This gives the kind of accessibility which can be developed for the electreonic goods with Scaling.