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Some of the logical solutions for overcoming the Interconnect bottleneck are:
7.7.10. Thermal Management due to excessive heating consequent to scaling.
Scaling reduces power dissipation per Gate but scaling increases the number of gates per chip. This coupled with higher speed scales up Chip Power Dissipation. Therefore Thermal Management becomes the central theme of Advanced Electronic Systyems.
In 1960, we had SSI chips which dissipated 0.1W to 0.3W per chip. These were cooled by Air and Liquid Cooling Techniques.
In 1980 we had BJT LSI and CMOS VLSI chips which dissipated 1 to 5W.
In 1990 CMOS VLSI were dissipating 15 to 30 W of heat.
CMOS μP chips at 1 to 2 W level were managed by heat sinks and heart spreaders.
When the dissipation level reached 2 to 3 W/cm 2 totalling to 300W at substrate level in multi-chip modules there we went for Liquid cooling.
Water cooled multi-chip modules evolved to refined indirect liquid cooling designs.
In 1990, third generation cooling modules were introduced which could handle 2 to 5kW dissipation in 225 to 1000cm 2 footprint.
7.7.10.1.Methods of Cooliing .
Some of the popular methods of cooling which were adopted were:
The method of cooling was categorized according to the product categories.
By 1997, IC power dissipation reached 100 to 150 W heatdissipation. Chip back side is allocated to heat removal. The heat removal may be done by any one of the following methods:
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