Figure 6.9. Non-planar Si/SiO2 interface as a result of LOCOS. The transition from Si to SiO2 is characterized by Bird’s Beak which has an adverse effect on Device Density.
- Buried Layer Diffusion
In fabrication of MC 1530 the first masked diffusion consists of (n+) type diffusion to provide buried layered to the collectors of the transistors . n+ type region is a heavily doped region which will be subsequently sandwiched between n type epitaxial collector and p type substrate as shown in Fig.(6.10).
The buried N+ region has the effect of shunting the high resistance collector body region thereby reducing the series resistance (r sc ) of the collector considerably. The reduction of r sc reduces V CE (sat) and increases the driving capabilities of the transistors.
Now as will be seen , after buried layer diffusion there are several heat treatment steps such as epitaxial growth, several oxidation steps and three diffusion steps. In all these proceeding steps, n+ buried layer should not be redistributed or out diffuse and should remain “stay put ” .Because of this requirement of ‘stay put’, Arsenic is used as buried layer dopant as it has a very low diffusion coefficient.
6.4.7_Passivation
Since the oxide layer is impervious to most contaminants that might influence the characteristics of a semiconductor, oxide layer serves as a protection for the semiconductor surface. The oxide layer is said to passivate the semiconductor surface. For this reason the oxide layer is regrown following each diffusion .
Now during masked diffusion impurities diffuse downward as well as laterally under the edge of the oxide as shown in Fig.(6.11) .
Because of lateral diffusion, the p-n junction meets the surface of the chip under the oxide layer hence again passivation prevents device deterioration due to surface leakages .
Thermal oxidation of wafer surface is done in a diffusion furnace as shown in Figure 6.5. A diffusion furnace contains of a central quartz tube where in a 20 inch central zone a flat temperature profile at a given temperature is maintained within ± ½ o c stability. This permits the batch production of I.C’s because hundred of wafers within this 20 inch zone can be simultaneously processed resulting in a tolerance of ±5 to ±10% in diffusion profile. Wafers on a quartz boat are pushed in the central flat zone of the diffusion furnace where temperature is typically maintained between 900 o c to 1200 o c. An oxidant such as oxygen gas or steam is passed through the central tube at a given temperature for a given time as determined by the thickness of SiO 2 . By this process 7000 o A thick SiO 2 layer is formed over the wafer. By the use of mask for n+ diffusion for buried layer, and photolithographic technique, suitable windows for buried layer diffusion i.e. for As diffusion are etched out.
Next fabrication step is masked diffusion of ‘As’ to form buried layers of the transistors used in MC 1530. Solid State Diffusion or selective diffusion of impurities into selected localized surface areas of the wafer is an integral part of I.C. technology. This can be achieved by ion implantation also.