9.19 Sspd_chapter 7_part 6_basic circuit concepts.

SSPD_Chapter 7_Part 6_Basic Circuit Concepts.

7.6.1. Sheet Resistance.

Referring to Figure 7.6.1 we see that:

Resistance of the slab along the longitudinal axis:

Therefore

Table 7.6.1 gives the typical values of the sheet resistance of the different layers of CMOS IC circuit.

Table 7.6.1.Typical values of the sheet resistance R S of MOS layers for technology generation 5μm, 2μm and 1.2μm. (Here 5μm, 2μm and 1.2μm imply the minimum feature size = channel length for the given technology . Consequently λ is 2.5μm, 1μm and 0.6μm for these three generations respectively).

7.6.1.1. Resistance calculation of N-Channel in 5μm Generation of Technology.

If L:W = 2λ:2λ then R _channel = R _sheet ×(L/W) = 1×10 ⁴ Ω..

If L:W = 8λ:2λ then R _channel = R _sheet ×(L/W) = 1×10 ⁴ Ω.×4 =4×10 ⁴ Ω..

With scaling, feature size has decreased and the pitch of metal interconnect has decreased. This has led to excessive RC time delay. To control this, metal interconnects are being replaced by Metal Silicides. The metal silicides or the refractory silicides are formed by depositing metal on poly-silicon and then sintering it. Though these have proved to be successful substitutes of metal interconnects the extra processing steps make it uneconomical.

With scaling the cross-sectional area of the metal interconnect decreases and current density increases. As this exceeds the limit of 1.5mA/mm, metal grains are pushed around and wire interconnects break. This is called migration. Silicides prevent electron migration.

With the latest generation of technology, silicides are being further replaced by copper interconnects.

7.6.2. Area Capacitance of Layers.

Parallel plate capacitance is given by the formula:

Where D=thickness of the dielectric between the plates;

A = cross-sectional area of the plate;

Absolute permittivity (permittivity) = ε ₀ = 8.85×10 ^-14 F/cm;

Relative permittivity of the dielectric in this case SiO ₂ = 3.9;

In VLSI design we express Capacitance per unit area = (pF/μm ² ). To obtain it in this form we have to the scaling factor as follows:

But Gate-to-Channel capacitance, C _g (pF/μm ² ) = 4×10 ^-4 , 8×10 ^-4 , 16×10 ^-4 ;

Therefore D = 88.5nm, 44.27nm, 22.1nm

Typical values are given in Table 7.6.2.

Table 7.6.2. Typical area capacitance values for MOS cuircuits.