1.8 The journey of i.c.technology from micro (1959) to nano (2009  (Page 2/4)

1. Low Threshold = 1V;
2. Negligible leakage current through Oxide;
3. High 2-D channel mobility;

The standard fabrication method was “Gate First”. In this method:

Gate Dielectric+Gate Electrode were laid first;

Source and Drain implanted;

Silicon is annealed to repair the damages that occurred during ion-implantation. High Temperature

became a problem for the new technology of HK-MG. So “Gate Last” technology was adopted which circumvented the annealing problem. This led to a paradigm shift in late 2004.

The new flow process was 45nm technology with High k + Metal Gate using Gate-Last strategy. Using this flow process in January 2006, 153Mb SRAM with 1 billion CMOS was built. Leakage gate current was reduced by a factor of 10. But there was sub-threshold leakage.

Scaling had reduced Threshold Voltage but reduced V _Th led to increased sub-threshold leakage which defeated the nanoWatt-logic objective. Each new generation of scaled down transistor would increase I _ON by about 30% but would lead to I _{sub-threshold} increase by 3-Fold. So at ULSI level, power efficiency and low leakage would be at premium rather than speed.

Table 9.The options at 45nm HK-MG CMOS Technology

The CMOS circuits are built between these two extremes.

PENRYN dual-core µP has 410mCMOS and PENRYN quad-core µP has 820 m CMOS. These are optimized for mobile applications, desk-top computers, 64-bit workstations and server applications.

IV.1.7.Mobility enhancement in strained Silicon.

[Mobility Enhancement, the next vector to extend Moore’s Law, Nidhi Mohata&Scott E. Thompson, IEEE Circuits&Devices Magazine, September/October 2005, pp.18-23]

Geometric Scaling has been driving IC Industry till date. Since 90-nm Technology generation was introduced, off-state leakage current and power density have made scaling a difficult and challenging job. New scaling vectors were adopted to meet this challenge. At 90-nm generation, mobility enhancement through uniaxial process-induced strained Si has emerged as the next scaling vector.

The theoretical formulations of carriers in 2-D inversion layer just below the insulator Gate:

where τ is the mean free time between two consecutive scatterings;

1/τ = scattering rate;

m ^* is the conducting electron effective mass.

Under strain, both m ^* and scattering rate reduce leading to enhanced mobility.

Uniaxial stress always provide higher current enhancement(1.46mA/µm and 0.88mA/µm for n-channel and p-channel respectively) as compared to that produced by biaxial stress(0.85mA/µm and 0.45mA/µm for n-channel and p-channel respectively). Hence in state of art technologies, Industries have adopted uniaxial stress. There are three state-of-art techniques:

1. A local epitaxial film is grown in the source and drain regions;
2. In the second technique we use a capping layer;
3. A dual capping approach.

FUTURE DIRECTIONS OF IC INDUSTRIES.

In the future we hope to go from 45nm technology to 32nm technology to 22nm technology to 16nm technology. The demand for high-speed transistors is increasing with the band-width required for telecommunication systems. Combining aggressive vertical scaling with reduced device parasitic, it has been possible to achieve 210GHz at room temperature using SiGe:C HBT Technology [“ A 210-GHz f _T SiGe HBT with a non-self-aligned structure”, Jeng, Jagannathan et al, IEEE ED Letters, Vol.22, No.11, Nov 2001] . Safe operating voltage measured is reasonable.