0.13 Dsd_chapter 6_mighty spartans in action_introduction.  (Page 2/2)

“Consumer applications ranging from cell phones, computers, TVs and even digital picture frames are incorporating wireless communication transceivers to implement broadband standards such as LTE(long term evolution), WiMAX and WiFi to provide wireless connectivity to the outside world. These transceivers rely on an analog interface in the digital baseband processor System-on-Chip (SoC) to connect with the RF block. This analog interface is constantly evolving to adapt to the different communications standards”.

We are going to use Spartan2 to implement Digital Systems desined using VHDL.

6.1. Design of BCD –to-Seven Segment Decoder-Driver.

This is available as a MSI_IC chip by the TTL code name 7447. This converts a binary code into its equivalent decimal magnitude and drives a Seven-Segment LED Display to display the corresponding decimal magnitude. We will give the behavioral architecture description and implement it on Spartan2.

VHDL codes of BCD-to-Seven Segment Decoder is the following:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity BCD_to_Seven is

__Port ( bcd : in STD_LOGIC_VECTOR(3 downto 0);

______ seven : out STD_LOGIC_VECTOR(7 downto 1));

end BCD_to_Seven;

architecture Behavioral of BCD_to_Seven is

begin

_________process(bcd)

_______________begin

____________________case bcd is

________________________when"0000"=>seven<="0111111";

________________________when"0001"=>seven<="0000110";

________________________when"0010"=>seven<="1011011";

________________________when"0011"=>seven<="1001111";

________________________when"0100"=>seven<="1100110";

________________________when"0101"=>seven<="1101101";

________________________when"0110"=>seven<="1111101";

________________________when"0111"=>seven<="0000111";

________________________when"1000"=>seven<="1111111";

________________________when"1001"=>seven<="1101111";

________________________when others=>null;

____________________end case;

_________end process;

end Behavioral;

On clicking “View Technology Schematic” we get:

Expanded RTL Schematic:

Expanded Technology Schematic gives:

Now we create the test bench and validate its functionality.

Since this is not a FSM (finite state machine), we need not define the Clock.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY Tb_BCD_to_Seven IS

END Tb_BCD_to_Seven;

ARCHITECTURE behavior OF Tb_BCD_to_Seven IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT BCD_to_Seven

PORT(

bcd : IN std_logic_vector(3 downto 0);

seven : OUT std_logic_vector(7 downto 1)

);

END COMPONENT;

--Inputs

signal bcd : std_logic_vector(3 downto 0) := (others =>'0');

--Outputs

signal seven : std_logic_vector(7 downto 1);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: BCD_to_Seven PORT MAP (

bcd =>bcd,

seven =>seven

);

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 10 ns.

-- insert stimulus here

bcd<="0000";

wait for 10 ns;

bcd<="0001";

wait for 10 ns;

bcd<="0010";

wait for 10 ns;

bcd<="0011";

wait for 10 ns;

bcd<="0100";

wait for 10 ns;

bcd<="0101";

wait for 10 ns;

bcd<="0110";

wait for 10 ns;

bcd<="0111";

wait for 10 ns;

bcd<="1000";

wait for 10 ns;

bcd<="1001";

wait for 10 ns;

wait;

end process;

END;

The output of the simulation is as follows:

As we can see in the above graphical figure, corresponding to binary code “0000” we have the output “0111111”. That is a,b,c,d,e,f LEDs are lit up and g is OFF. Hence we get a figure:

This Seven-Segment Display is an integral part of Digital Meters, Digital Clocks and Digital Instruments. The Seven-Segment Display with the BCD-to-Seven Segment Decoder and N-Modulus Decade Counter is the basic sub-system of Digital Clocks. This will be taken up later on in the chapter while designing hour-minute-second clock.