Refering to the circuit in Fig. (6.26) we see that there are eight different collector voltages and four different Diode anode voltages:
1) input darlington pair Q 1 and Q 2 correspond to one collector voltage,
2) input darlington pair Q 4 and Q 5 correspond to second collector voltage,
3) Q 6 , Q 8 and Q 12 correspond to the third voltage namely Vcc collector voltage since they are in CC (Common Collector) mode,
4) Q 3 , Q 7 , Q 10 , Q 11 , Q 13 correspond to fourth, fifth, sixth, seventh, and eighth collector voltages;
5) there are four different diode anode voltages corresponding to D 1 , D 2 , D 3 , D 4 .
Corresponding to these twelve different quiescent voltages which are Vcc or less but always greater than -V EE , we have twelve isolated islands as seen in Fig. (6.27) where each isolated island is marked by thick border lines.
The isolated islands containing Q 6 , Q 8 and Q 12 and connected to Vcc contains all resistances R 1 to R 11 and R X and R Y . Resistances are realized by an elongated strip of p diffusion and any point on the resistances is less than Vcc or at most Vcc. In order that resistances may be isolated from n epi layer and hence from one another, n epi layer i.e. the isolated island must be at most positive potential i.e. Vcc. Then only all resistances will be reverse biased with respect to the n epi layer.
Fig(6.26) Complete circuit diagram of MC 1530/31 chip, with the points of different contact pads marked
Fig(6.27) Twelve isolated islands and placement of transistors, diodes and resistors on the islands have been indicated. The detailed structure of the devices have not been given.
In Fig. (6.27) complete layout of MC-1530 is given. In the chip layout following are the contacts connected to the header leads:
Contact(a) connects substrate to contact(4) which is held at -V EE .______________________Contact(b) connects the isolated island containing resistances and CC transistors to contact(6) which is held at +Vcc._________________________________________________________________________________________________________Contact(1’) and (2’) are input connections for MC-1530, ___________________________________________Contact(1) and (2) are input connections for MC-1531__________________________________________________________Contact(5) is output,_________________________________________________________________________________________Contact(3) is ground,_________________________________________________________________________________________Contact(7) , (8), (9)and (10) are monitoring points at V B11 , V E8 , V C5 , V C1 respectively.
In MC 1530-31, each transistor and diode configuration of transistor contains buried layers. The epilayer is 0.5 Ω cm. This allows BV CEO to be 20V. But because of buried layer the collector series resistance (r sc ) or saturation resistance are less than 50Ω. Hence with V CC ± 9V, an output swing of 16V p-p is achieved without endangering the output transistors Q 13 , Q 12 and at the same time r sc does not affect the ability to drive loads down to 500Ω.
In the design of MC1530-31, the critical d.c. levels are kept a function of resistor ratios and not of absolute values. This is because in I.C. technology, diffused resistance ratios with much closer tolerance (typically 5 to 6 %) can be achieved as compared to the tolerance of absolute values (30 to 50 %). That is matching tolerance is much narrower than absolute tolerance. Therefore output d.c. level (V 0 ) is a function of only resistor ratios – not of the absolute value of any resistor or of the beta of any device of the circuit. V o is given by Eq.(6.5)