In first phase of I. C. Technology where Photolithography was used, a resolution of 10 µm could only be achieved. This put a very low limit on the system complexity which could be integrated within the chip mainly because of a low packing density. Hence only circuits of a fair degree of complexity could be integrated. This was known as Small Scale Integration (S. S. I.).
But with the development of Deep Ultra Violet Lithography and Ion Beam Processing (such as Ion Beam Milling and Ion Implantation), which afford submicron resolution and with the development of MOS technology, much higher packing density has become physically realizable. This has greatly raised the limit on system complexity which can be Integrated. Now it is possible to integrate a fully functional block. This level of system complexity when integrated gives rise to Medium Scale Integration (MSI) chips, Large Scale Integration (LSI) chips and Very Large Scale Integration (VLSI) chips.
Examples of S.S.I., M.S.I., L.S.I. and V.L.S.I. are given in Table (6.1).
Table (6.1) SSI, MSI, LSI and VLSI/ULSI Chips.
| S S IQuad 2 inputSN 5400 | M S IDecade CounterSN 5490 | L S I1024-bit Shift register and 4K(4096 bit) memory elements | VLSI/ULSIIntel8086/Pentium IV | |
| Chip area(sq. mils)1 mil=25 microns | 3000 | 5750 | - | ½ cm x½ cm |
| Number of components | 36 | 102 | More than 100 gates | 10 5 to40 million CMOS |
The ultimate packing density achieved to this date (2011) is 1.3 billion devices in dual core Itanium 2 processors chip manufactured by INTEL. These are examples of Ultra Large Scale Integration (ULSI). LSI techniques have made possible small modern hand held calculations, microprocessor based microcomputers, powerful digital computers in relatively small sizes and the integration of much of the electronics within audio amplifiers and televisions sets.
As of 2005, a IC Chip fabrication foundry facility costs over $1 billion . It has the following features:
- Wafers are 300 mm diameter;
- 65nm technology is gradually being replaced by 45nm technology;
- Deep Ultra Violet (193nm) immersion Lithography is being used;
- Aluminum interconnects are being replaced by copper interconnects to overcome the problems associated with lateral scaling;
- Low-K dielectric insulator is being used for the Cu-interconnects overlay surface so as to maintain a high velocity of prorogation;
- Silicon on Insulator is being used to reduce the parasitic capacitances;
- Strained Silicon directly on Insulator is being used for higher electron mobility in 2D channel.
The development of Liquid phase and Vapor phase epitaxy has made Gallium Arsenide technology commercially feasible. Metal Organic Chemical Vapor Deposition (MOCVD), a low cost technology, and Molecular Beam Epitaxy, Ultra high vacuum technology, are further developments in the direction of GaAs technology.
In Table (6.2) a comparative study of GaAs , Si and Graphene is made.
Table (6.2) A comparative study of GaAs, Si and Graphene.
| Band Gap300K | Mobility of electrons300K_cm 2 /(V-sec) | Mobility of holes300K_cm 2 /(V-sec) | Intrinsic ConcentrationAt 300K(number/cc) | |
| Si | 1.12eV(Indirect) | 1500 | 600 | 1.45×10 10 |
| GaAs | 1.43eV(direct) | 8500 | 400 | 9×10 6 |
| Graphene | Zero-gap semiconductorOr semi-metal | 200,000 | No holes | 10 12 /cm 2 |