6.1 Differential phase shift keying

The phase lock loop provides estimates of the phase of the incoming modulated signal. A phase ambiguity of exactly $\pi$ is a common occurance in many phase lock loop (PLL) implementations.

Therefore it is possible that, $\stackrel{}{}=+\pi$ without the knowledge of the receiver. Even if there is no noise, if $b=1$ then $\stackrel{}{b}=0$ and if $b=0$ then $\stackrel{}{b}=1$ .

In the presence of noise, an incorrect decision due to noise may results in a correct final desicion (in binary case, when thereis $\pi$ phase ambiguity with the probability:

Consider a stream of bits $a_n\in \{0, 1\}$ and BPSK modulated signal

In differential PSK, the transmitted bits are first encoded $b_n=a_n\mathop{\mathrm{xor}}{b}_{n1}$ with initial symbol ( e.g. $b_0$ ) chosen without loss of generality to be either 0 or 1.

Transmitted DPSK signals

The decoder can be constructed as

If two consecutive bits are detected correctly, if ${\stackrel{}{b}}_n=b_n$ and ${\stackrel{}{b}}_{n1}=b_{n1}$ then