0.3 Dsd_chapter 2_basics of plds  (Page 3/3)

Let us examine Figure 9 closely:

Q3 and the NMOSs in that ROW are Load FETs. Here Drain and Gate of NMOS have been shorted. Hence Q3 and its corresponding elements act as loads of the bit-lines Y0,Y1,Y2,Y3.

NMOS has the advantage that it can act in following manners:

1. as a Capacitor when you operate between Gate and Source;
2. as three terminal active element;
3. as a non-linear two terminal resistance when Gate and Drain are shorted together.

NMOSs in the Word-lines act as MEMORY ELEMENTS.

All Bit-lines are at HIGH level. Because Vdd = 5V is being applied to all Bit-lines and all bit-lines at the other end is simply hanging.

When W0 goes HIGH, the intersections of Y1, Y2 and W0-line have no NMOS. Y1 = ‘1’ and Y2 = ‘1’ state continues as it was before.

At the intersection of Y0 and Y3 we have Q2 and Q4 NMOSs. Their Gates are connected to W0-line which is presently held HIGH at 5V>Threshold Voltage of NMOS. Hence Q2 and Q4 turn ON and provide a short to Ground. Therefore Y0 = ‘0’ and Y3= ‘0’.

Here we are following ACTIVE-LOW Logic. Ordinarily bit-lines are at ‘1’ and when ACTIVE they go LOW or go to ‘0’.

Thus with 0000000000 address word applied to the address bus of the given ROM, W0 gets selected and ‘0110’ ,which is stored in the ROM memory space, gets READ out.

The following Table 1 gives the binary bits stored in locations selected by W0,W1,W2 and W500 word-lines.

Table 1. The Word address and the bit-outputs.

Here the Bits stored are pre-programmed and cannot be changed unless we find some methods to construct NMOS and omit NMOS at the 1024×4 ROM Memory Cells.

What we have shown is a Factory programmed ROM. Field programmed ROM had to wait for several years before it was introduced as Field Programmable Devices.

In the above example Y0 bar or Y0′ = W0 +W2;

Y1′ = W1; Y2′ = W1 + W2 + W500; Y3’ = W0 + W500;

By inverting the bit-lines we obtain SOP Logic Functions.

ROMs do not minimize the gates for a given CODE-conversion.

Suppose the customer wants me to design ‘BCD to 7-Segment decoder-driver’.

What this means that :

Table 2. Decoding of BCD to Decimal NUMERIC value.

In Figure 10 we have shown the construction and the composite structure of 7-SEGMENT DISPLAY. In Figure 10 it is also shown as to which LED should glow corresponding to a decimal value. From this knowledge we can construct the following Table 3 for code conversion.

Figure 10. Construction of Common Anode 7-Segment Display.

Table 3. Conversion from a BCD to a Seven-Segment-Display Code.

Since input code is 4 bits therefore there are 2 ⁴ = 16 word lines hence Table 3 must have 6 extra Word-lines i.e. W10, W11, W12, W13, W14, W15. Corresponding to these 6 Word-lines there are some arbitrary SYMBOL displays depending upon the convenience of the Designer.

If all 16 Word-lines are considered then the bit-line Y0 will be by inspection of the Table:

Y0= W1 + W4 + W6 + W10 + W11 + W14 + W15;

By replacing the Word-line by their corresponding Product Term we get:

Y0 = D′C′B′A + D′CB′A′ + D′CBA′ + DC′BA′ + DC′BA + DCB′A′ + DCBA′ + DCBA.

By minimization technique we obtain:

Y0 = D′C′B′A + CA′ + DB;

Similarly minimized expressions can be obtained for all the remaining 6 bit-lines.

If using the minimized expressions for Y0, Y1, Y2, Y3 Y4, Y5, Y6 we build the decoder-driver then almost 20% saving in component count takes place as compared to a decoder-driver built by ROM. It can be even more. But this will require extra man-hours for minimizing and designing. If the demand can justify this extra cost then one could go for these especially designed and optimized circuits. These circuits are called ‘Application Specific Integrated Circuits’(ASIC). The ‘BCD to 7 Segment decoder-driver’ presently available in the market by the component code 74HC4511 is one such ASIC circuits.