0.4 Digital system design_chapter 2_section 2_wishlist of digital

Digital System Design_Chapter 2_Section 2_Wishlist of Digital System Designer.

The wishlist of Digital System Designer is to create a PLD where he downloads a programme and gets the PLD configured for a certain number of functions. With passage of time a few more functions are to be added and some existing functions are to be omitted. He would like to modify his programme and reload it on the same PLD. Economy-wise this would make sense. But this requires that he has Electrically Erasable and Reprogrammable PLD. This requires that it should be field-programmable.

In 1956, at the request of US Air-Force, Scientists of ARMA Division of American Bosch Arma Corporation, Garden City, New York, developed a User Programmable ROM akin to Diode Matrix shown in Figure 6 of Chapter 2_Section 1. The fresh ROM had a diode connected at all intersections. It implied state HIGH or ‘1’ in all memory cells. The user could retain or omit the DIODE at the intersection as his design need be. By applying a High Voltage Pulse of 30V which is not used in Digital Systems, the user could burn the whiskers of the Diode and thereby “burn” / “Zap” / “blow” open the given diode. This would give ‘0’ state in that particular Memory Cell which lies at the given intersection. This way by burning the requisite set of memory elements namely the diodes at the intersections, the desired functional relationship can be achieved. Once the requisite diodes are blown out, the functional relationship is unalterable. Hence this was called One-Time User Programmed ROM.

In1971, Intel Scientists at Santa Clara, California, developed Erasable Programmable ROM (EPROM). This new device was based on a special double-gate NMOS referred to as Floating-Gate Avalanche-Injection MOS(FAMOS). This double-gate NMOS is shown in Figure 11.

Figure 11.Floating Double Poly-silicon gate structure NMOS used in EPROM

In Figure 9 of Chapter 2_Sec 1, we place such Double-Gate NMOS at all intersections as shown in Figure 12.

Figure 12. EPROM using Double-Gate NMOS.

Before user programming, FAMOS (Double-Gate NMOS) is present at all intersections. Any Word-line going HIGH will place 0s at all the four Bit-lines. Hence effectively EPROM comes with 0s stored in all memory cells. When the user applies 25V pulse between Gate2 and Drain, a high electric field is created in the depletion region of the p-n junction of the Drain-substrate. This electric field is in excess of the critical field. This results in Avalanche Breakdown. This creates a large reverse current. The electron component of this breakdown current is accelerated towards Gate2. It penetrates the thin oxide region and gets accumulated on Gate1. Gate 1 effectively becomes negatively charged hence 5V at Gate2 is no more able to turn this transistor ON. Hence effectively the NMOS at that intersection is disabled and state ‘1’ is permanently stored in that cell. Thus by application of 25V at the requisite intersections’ FAMOS, the transistor is disabled and state ‘1’ is permanently stored giving rise to the desired Boolean Function. Because of SiO2, charges accumulated on Gate2, do not discharge for 10years and longer. The ‘1s’ stored by application of 25V at Gate2s can be easily erased by exposing the ROM to Ultra-Violet light. UV light makes the SiO2 slightly conducting thereby providing a path for leakage of charge accumulated on Gate1. Thus all disabled NMOSs are enabled and this restores EPROM to all ‘0s’ states . This can once again be reprogrammed and reconfigured. But this requires long exposure time in excess of 2 minutes for complete eraser. Hence Electrically erasable and programmable ROM(EEPROM) became the need of the hour.