8.9 Sspd_chapter 6_part 6_mos ics fabrication technology_to be  (Page 2/2)

The P+ source of PMOS in N-tub and N+ source of NMOS in P-Tub together with N-Tub bulk and P-Tub bulk behave as cross-coupled BJTs.

P+ source of PMOS in N-tub, N-Tub and P-Tub behave like a parasitic PNP BJT where P+ is the emitter.

N+ source of NMOS in P-Tub. P-Tub and N-Tub behave like a parasitic NPN BJT where N+ is the emitter.

The cross coupling of the two gives rise to a four-layer device namely SCR as shown in Figure 52.C. If this SCR fires, because of the voltage drop in N-tub bulk resistance and because of voltage drop in P-tub bulk resistance, then it will provide a low impedance path from Positive Vdd supply to the ground leading to irreversible destruction of the CMOS structure. To prevent this from happening we use the second option. The active devices are formed in lightly doped epitaxial layer. This epitaxial layer is deposited over buried layer. N+ buried layer shorts N-tub bulk resistance and P+ buried layer shorts P-tub bulk resistance. This prevents the firing of SCR.

The process steps for the second option.

We start from Step 1 as shown in Figure 6.53. On P-Type substrate SiO2 , 40nm thick, is grown. That is followed by Si3N4, 80nm thick.. Lastly it is covered by 200nm thick KPR layer.

Mask 1 defines the buried layer area namely N+ type buried layer as shown in Figure 6.54. We want N-type buried layer with high doping concentration. So we want a donor type dopent which does not out-diffuse in subsequent thermal cycles. Antimony and Arsenic both qualify for buried layer diffusion but Arsenic has higher solid solubility therefore we go for Arsenic in a high dose implant of 10 ¹⁵ cm ^-2 at accelerating voltage of 50kV. This energy of 50keV is sufficient for implanting it beneath the 40nm thick Oxide layer.

After N+ type buried layer diffusion, we strip off the fixed KPR and carry out drive-in for 2 hours at 1000°C, with 60 minutes of this in steam ambient for LOCOS oxidation. Due to drive-in the buried layer is driven to depth of 2microns and just over the buried layer we get a local thick layer of SiO2 400nm thick. The cross-sectional view at this point is shown in Figure 6.55.

This high temperature drive-in plus LOCOS oxidation accomplishes the following objectives:

1. It drives in the buried layer to 2 micron depth;
2. Thick oxide layer of 400nm is achieved just over the buried N+ layer because of the masking effect of Si3N4 layer;
3. This LOCOS oxide allows the same mask to be used for defining both N+ buried layer as well as P+ buried layer and the LOCOS oxide allows self alignment between the two buried layers;
4. Finally this step creates a step in the silicon surface at the edges of the N+ buried layer because oxidation consumes silicon. This step will act as the foot print of the buried layer in later processing.

After the furnace operation, Si3N4 is dry etched in Fluorine Plasma Chamber. Now

we do the ion implantation of P+ buried layer. The thick oxide layer (400nm thick) over N+ buried layer acts as the shield against P+ Boron ion implant but thin oxide layer (40nm thick) elsewhere allows the P+ Boron implant to enter the silicon surface. An implant dose of 10 ¹⁴ cm ^-2 at accelerating voltage of 50-75 kV. The implant for P+ buried layer is Boron. A lower implant dose is chosen because Boron has a higher diffusion coefficient and to prevent out-diffusion in subsequent thermal cycles a lower implant dose helps. The cross sectional view at this point is as shown in Figure 6.56.

A simple drive-in cycle is carried out for several hours at 1000-1100°C in inert ambient of Nitrogen or Argon. LOCOS oxidation is not required. The resulting structure is shown in Figure 6.57.

Now we require lightly doped N-tub and P-tub. Lightly doped N-tub and lightly doped P-tub are required for fabricating PMOS and NMOS respectively because of the following reasons:

1. The light doping reduces the junction capacitances hence improves the frequency response;
2. It gives a better control and a lower threshold voltage or turn on voltage.

Threshold voltage expression is given in Equation 6.21.

Heavy doping increases the surface potential and hence increases the turn-on voltage.

Now this lightly doped region cannot be achieved by counter doping and by compensation because the buried layer is of the order of 10 ¹⁹ /cc and active regions have to be of 10 ¹⁶ /cc. Therefore we choose the option of lightly doped epi-layer.

We etch out the SiO2 layer completely and grow intrinsic epitaxial layer of Silicon to a thickness of 2 to 3 microns. The cross sectional view is as shown in Figure 6.58. The step at the boundary of the buried layer has propagated upward into the epitaxial layer also and it will help in subsequent alignment of the masks.

After this the steps carried out in Figure 6.44 or in Figure 6.45 to grow the field oxide and the steps carried out Figure 6.46 , in Figure 6.47 and in Figure 6.48 to grow the twin tubs and drive them in are carried out. The drive-in for both the tubs are carried out in a way that the twin-tub are linked up with one-another and the buried layers are also linked up. The final structure appears as shown in Figure 6.59.

It may be noted here that this option of buried layer plus epitaxy has required only one more Mask but many more steps.

Now we are ready for the final fabrication of complementary symmetry MOS devices.