Table 6.6 and Table 6.7 shows the strides taken in microminiaturization. This has meant a lot of energy, resources and time invested in technology improvement to achieve this kind of scaling.
As of 2004, current PC processors are fabricated at the 130 nm and 90 nm levels, with 65 nm chips being announced by the end of 2005. A decade ago, chips were built at a 500 nm level. Companies are working on using nanotechnology to solve the complex engineering problems involved in producing chips at the 45 nm, 30 nm, and even smaller levels—a process that will postpone the industry meeting the limits of Moore's Law.
Moore's Law of Integrated Circuits was not the first, but the fifth paradigm to provide accelerating price-performance. Computing devices have been consistently multiplying in power (per unit of time) from the mechanical calculating devices used in the 1890 U.S. Census, to Turing's relay-based "Robinson" machine that cracked the Nazi enigma code, to the CBS vacuum tube computer that predicted the election of Eisenhower, to the transistor-based machines used in the first space launches, to the integrated-circuit-based personal computers. In the process of miniaturization we have met with seemingly unsurmountable obstacles which in due course of time with new technological breakthroughs and innovations have become surmountable.
These technological breakthroughs and innovations have meant that R&D, manufacturing, and test costs have increased steadily with each new generation of chips. As the cost of semiconductor equipment is expected to continue increasing, manufacturers must sell larger and larger quantities of chips to remain profitable. (The cost to "tapeout" a chip at 0.18um was roughly $300,000 USD. The cost to "tapeout" a chip at 90nm exceeds $750,000 USD, and the cost is expected to exceed $1.0M USD for 65nm.)
"What we didn't realize then was that the integrated circuit would reduce the cost of electronic functions by a factor of a million to one," Kilby said.
Placing several million transistors on a piece of silicon the size of a fingertip is intricate and exacting. Precision associated with chip manufacturing is measured in microns and increasingly in fractions of microns. A micron is one-millionth of a meter, or about one one-hundredth of the diameter of a human hair. Maintaining this level of precision demands chip production environments that are 1,000 times cleaner than today's cleanest surgical operating rooms.
Challenge number 1: “Clean Rooms for IC fabrication”.
Challenge number 2: “Patterning or Lithography”.
Challenge number 3:”Transistor Options”. Classical scaling ended in 2001.
Challenge number 4:”Interconnect options”.
Challenge number 5:”High density memory beyond SRAM is required in today’s devices.”
Challenge number 6:”System Integration”.
Solving these problems INTEL is moving to 32nm technology.
1960s was dominated by Bipolar Technology and TTL Logic Gates operating at 5V.
The earliest challenge of 1960s was the production of electrically stable MOS devices. By the end of 1960s electrical stability was achieved by using Phosphorous doped SiO 2 often known as P-Glass.