Phosphorous has been added to protect the active devices from Na + ions and Boron has been added so that the glass can reflow at a lower temperature. This heat cycle and reflow is required to even out the undulations after conformal deposition. But even after this reflow the undulations are not completely removed and planarization problem remains.
Planarization is done either by resist etchback technique or by CMP method. Resist etchback technique is as follows:
In resist etchback technique we spin KPR over the entire wafer surface creating a plane KPR surface at the top. All the hills and valleys are filled and a horizontal level of KPR is left at the top. Remember water seeks its own level. Now we can find a Oxygen Plasma etching combination which etches SiO 2 and KPR with equal ease. Allow this physical etching to continue until the lowest level in SiO 2 is reached. At this point stop the etching. In effect we have achieved complete planarization as shown in Figure 6.77.
In CMP method the wafer is put face down on a polishing machine and it is polished flat in a high-pH silica slurry. This also results in same planar surface as shown in Figure 6.77.
6.6.6.1. Vias between Metal Level_1 and contact pads of the Active Devices.
We use Mask 12 to define the vias through which contacts will be made between Metal Lavel_1 and contact pads of the Active Devices as shown in Figure 6.78.
After making the windows selectively through Mask 12, we etch SiO 2 in a plasma. After selectively etching the oxide in the vias, the fixed KPR is stripped off by oxygen plasma etching. We get the structure as shown in Figure 6.79.
We wish to maintain the planar surface as we add Metal Level 1 and Metal Level 2. There are many process flows for doing this but the commonest process flow is as follows:
A few tens of nm thick Ti/TiN bilayer is blanket deposited over the entire wafer area. This can be done by sputtering or by CVD. This bilayer provides a good adhesion to the SiO 2 and other underlying areas materials present in the structure at this point. The TiN acts as a barrier layer between upper Metal Level 1 and lower Local Interconnect layers ewhich connect the active devices. After the bilayer deposition we do tungsten(W) blanket layer deposition by CVD. A typical reaction might be:
WF 6 +3H 2 → W + 6HF
The resulting structure is shown in Figure 6.80. We do CMP to remove W and Ti/TiN from all the portions except the vias as shown in Figure 6.81. The resulting plane surface will be the base over which the metal layer will be deposited and interconnection pattern of first Metal layer will be etched out.
Next Metal deposition is done on the entire wafer surface as shown in Figure 6.82.. The metal is Aluminum. Aluminum has a small percentage of Si and small percentage of Cu. Si is soluble in Al and if Si is not present in the Metal Layer it will be absorbed from underlying Si rich layers. Absorption may cause contact problems as well as reliability problems. Hence it is preferred to consciously add Si to Metal Layer 1. Cu is added to prevent electronmigration from Al thin films. Electronmigration will lead to break in the interconnection and hence create yield problem. Electron flow in te metal line , over time, can cause the metal atoms to migrate along crystal grain boundaries or along the metal/dielectric interfaces in quasi-random manner. Voids may develop in the metal lines as a result and cause the line resistance to increase or even become open circuited. So Copper has replaced Al as the interconnect material in advanced ICs.
Copper has excellent electronmigration reliability and 40% lower resistance than Al. Copper may be deposited by plating or CVD. Because dry etching of Cu is difficult, copper patterns are defined by a damascene process. This will be discussed in a later section.
Al Metal Layer is shown in light sky blue colour. By photolithography technique and Mask 13 the interconnection pattern in the Metal Level 1 is etched out as shown in Figure 6.83.
After the Metal Interconnect Pattern has been etched out, fixed KPR is stripped and again the entire wafer surface is covered with CVD Oxide layer. This Oxide layer is planarized, vias are defined by Mask 14 and vias are etched out. Now Metal Layer 2 is deposited again by sputtering and interconnect pattern is defined using Mask 15 and the redundant portion of the Metal is etched out by plasma etching. The final interconnect pattern is covered by Pasivation layer either of SiO 2 or Si 3 N 4 . This top layer is used to protect the chip during mechanical handling while packaging. This passivation layer will also protect against ambient contamination (Na + and K + ).
After the final processing step, the wafer is subjected to a low level thermal cycle of 400 to 450°C for about 30 minutes in forming gas (10% H 2 in N 2 ). This helps alloy the metal contacts to the contact pads through vias. This also helps reduce the electrical charges associated with Si/SiO 2 interface. The resulting structure is shown in Figure 6.84.
“To bulid complex and dense circuits , the multi-level metallization structure shown in Figure 6.84 is routinely employed. Up to about 10 metal layers may be used. The metal thickness may range from a small fraction of a micron to several; microns. The thinner interconnects route signals while the thicker layers serve as power lines.”
“The dielectric material between the metal layers used to be SiO 2 . It has been supplemented with low-k dielectrics which often contain carbon or fluorine, and are designed to have much lower dielectric constants(k) than SiO 2 . Lower k leads to lower capacitances between interconnects. This is highly desirable because capacitance in a circuit slows down the circuit speed, raises power consumption and introduces cross talk between neighboring interconnect lines.
Since a large number of metal layers and process steps are involved, making the interconnects consumes a large part of the IC fabrication budget . This part of the fabrication process is called the back-end process . In contrast , the steps used to produce the transistors are called the front-end process .”
[ The quotes have been taken from the following book:
“Modern Semiconductor Devices for Integrated Circuits” by Chenming Calvin Hu, Pearson 2010]