Table 6.13. Gate Oxide Thickness vs Channel Length
for different generations of Technology.
| L(micron)(Poly-Si) | 0.35 | 0.25 | 0.18 | 0.13 | 0.10 | 0.07 | 45nm(MG-HK) | 32 | 22 | 15 |
| T OX (nm) | 8 | 6 | 4.5 | 3.4 | 2.5 | 1.9 | 4 | 3.4 | 2.5 | 1.2 |
| I off (nA/micron) | 0.5 | 3 | 10 | 40 | 100 | 200 | 300 | 300 | 300 | |
| Fringing Capacitance_C f * (fF/µm) | 0.60 | 0.71 | 0.61 | 0.74 | 0.78 | 0.74 | 0.85 | 1.04 | 1.01 | |
| Transistor delay_τ(ps) | 6.26 | 4.56 | 2.55 | 1.88 | 1.46 | 1.15 | 1.23 | 1.47 | 1.45 | |
| Sheet resistance of heavily doped PolySi(ohms per sq) | 300 | 250 | 200 | 200 | 200 | 200 | 200 | 200 | 200 |
Table 6.13 is based on projection and simulation for nodes at 45nm and below. For nodes above 45nm, the Table is based on actual experimental work. It is clear that at 45nm and at greater scaling, we get counterscaling effects. Because of increased fringing capacitance, transit delay deteriorates beyond 45nm technology. But with emergence of multicore processors, number of available transistors is more important than making them faster. Hence scaling will continue to be used even though it is becoming counter productive.
6.6.3.3 LPCVD of PolySi for Gate contacts.
By Low-Pressure-Chemical-Vapour-Deposition techniques Si is deposited over the entire area of SiO2 as shown in Figure 6.62. Silane is passed over the wafer and at 600°C it decomposes into Si and H2. Si precipitates over SiO2 surface. Since the substrate of SiO2 is amorphous hence LPCVD Si is PolySi.
300 nm to 500 nm thick PolySi is deposited over the entire wafer area. By unmasked ion-implant of Arsenic or Phosphorous , PolySi is heavily doped provideng sheet resistance of 300 ohms per square. The N-type ion-implant has a dose of 10 15 /cm 2 at an energy of less than 50keV so that it implants the PolySi but does not penetrate through to the underlying gate oxide. In subsequent thermal cycles N-type donor dopent will diffuse and evenly distribute throughout the PolySi contact.
In some PolySi deposition systems, in-situ doping is done while LPCVD is carried out. In this case ion-implant step of heavy doping is not required.
6.6.3.4. Formation of PolySi Gate contacts in MOS active areas.
Using KPR and Mask 6, the PolySi is retained in Gate areas of MOS and PolySi is etched out from the remaining portions of the wafer as shown in Figure 6.63. This again is dry plasma etching using chlorine or bromine based plasma.
Heavily doped PolySi is not only used as Gate contacts but also as local interconnects between NMOS and PMOS gate contacts but these cannot be used for long interconnects like metal interconnections. PolySi has relatively high sheet resistance (300Ω/square) as compared to that of Metal interconnects which is only 0.1Ω/square. The RC delays of long poly lines make these long poly lines unacceptable in IC fabrication.
While etching PolySi we want selectivity as well as anisotropy. Selectively will ensure that only PolySi is etched and not the underlying SiO2 and anisotropy will ensure that there is no undercutting. Now these are two conflicting requirements. There has to be a trade off between the two in our plasma etching systyems.
The remaining fixed KPR is removed by stripper solution or by oxygen plasma etching.