The journey of i.c.technology from micro (1959) to nano (2009) era

The Journey of I.C.Technology from micro (1959) to nano (2009) era_ABSTRACT.

Keyword: Monolithic Planar Technology, Wafer, epitaxial layer, fabrication, photolithography;

Summary: This is the abstract of the main article named as above.

ABSTRACT:

The discovery of ELECTRON by J.J. Thomson started a series of inventions which was to culminate into Solid State Bipolar Junction Transistor (invented by Shockley, Bardeen and Brattain) in the year 1948. This marked the advent of the era of Solid State Technology . Solid State Technology laid the foundation of Silicon Monolithic Planar Integrated Circuit Technology in 1959. In 1960 first high temperature epitaxial based BJT IC came into market. This kick started a process of Information Revolution leading to the third wave of civilization or post industrial civilization. By 1970 four- bit Microprocessor Chip uP4004 was introduced. The advancement of IC Technology led to exponential increase in packing density as well as in electrical performance. From 1971 to 2001, Small Scale Integrated Chips evolved to Medium Scale Integrated Chips to Large Scale Integrated Chips to Very Large Scale Integrated Chips to the present Pentium IV which is Ultra Large Scale Integrated Chips packing 42 million CMOS Chips. This increase in packing density was enabled by the advancement the lithography technique. In 1966 emulsion mask patterns were contact printed on 200mm wafer with the smallest feature size of 25µm. In 2007 using Deep Ultra Violet(DUV)193nm immersion Lithography, 30nm ±6nm feature size are imprinted on 300mm wafer. We moved from Wet Processing to Dry Processing ( reactive ion etching) or Ion beam Processing , Diffusion was replaced by Ion Implantation , Mask Making Techniques were improved and automated, preparation of master art work was automated using computer, step and repeat cameras were replaced by contact cameras, photolithography used ultra violet light for exposing the Kodak Photo Resist, UV light lithography was replaced by Deep UV lithography and now it is in process of being replaced by Extreme UV laser beam lithography as the feature size became smaller, Liquid Phase Epitaxy and Chemical Vapour Phase Epitaxy developed into Metal Organic Vapour Phase Epitaxy , new materials were introduced for interconnections ( such as silicides and copper ) and Poly- Silicon for gate contacts, the dielectric material used in gate silicon dioxide is being replaced by hafnium oxide which has a higher dielectric strength and higher k , planar technology is being replaced by trigate technology where gate contact is on the top as well as on the side walls of the oxide layer thereby increasing the contact area, parasitic were reduced by shallower junctions, smaller feature size and oxide side walls and by using insulator as the substrate for instance silicon on sapphire. One more innovation was Lightly Doped Drain for improving the reliability of the MOS devices. FET depends on leading edge lithographic dimensions(45nm) but BJT depends on vertical base widths which has reached 10nm. BJT has structural flexibilities in minimizing the parasitic. It has higher trans-conductance, high self gain, low 1/f flicker noise and better V _BE matching. All these factors make BJT the device of choice for demanding applications. While microlevel BJT scaled down to nano level structure, new problems arose due to shallow EB junction, band gap narrowing in emitter due to doping concentration exceeding above 10 ¹⁸ /cc and high sheet resistance of the base layer. These problems were tackled by using heavily implanted PolySi layer used as emitter contact . SiGe Hetro Bipolar Transistors(HBT) hold the key to realizing high speed wire-line and wireless communication circuits and systems. Marriage of Si Technology and Bandgap Engineering Methods of III-V Compund Semiconductor which is broadly called SiGe based bandgap engineering is Si Heterostructure Bipolar Technology (SiGe HBT). This was made possible by Low Temperature Epitaxy(LTE). Scaling strategy was used here also for exponential growth in the packing density and electrical performance of devices. To reduce the time delays, base width and collector widths have to be reduced and I _C must be increased which requires Kirk Effect should be pushed to higher Current Densities. This is achieved by increasing Collector Dopent Concentration. Hence Selectively Implanted Collector (SIC) is introduced. Decreasing the distance between SIC and extrinsic base implant will increase the overlap i.e. C _CB OL. This has to be minimized. This is achieved by Raised Extrinsic Base structure. An optimization in Ge profile in SiGe base layer has to be done inorder to get the full advantage of increased base doping in HBT. Today SiGe HBT are surpassing GaAs HBT. The integration of SiGe HBT with CMOS is BiCMOS. BiCMOS reduces the cost of mobile consumer products, advance high BW wireless communication and collision-avoidance automobile radar. BiCMOS lead to VLSI, ASIC&Si based RF SOC(System on Chip) solution. Hence SiGe/SiGeC and BiCMOS is becoming the technology of future. The strategy of Sidewall oxidation and Silicon-on-Insulator (SOI) is adopted for reducing the parasitic capacitances and improving the frequency response. P ⁺ isolation diffusion is replaced by trench isolation. Shallow Trench Isolation (STI) is achieved by Reactive Ion Etching(RIE). This considerably helps reduce the parasitic and helps improve the speed. Since 90-nm Technology generation was introduced, off-state leakage current and power density in CMOS have made scaling a difficult and challenging job. New scaling vectors were adopted to meet this challenge. The new scaling vector was Mobility enhancement through strained Si and novel structure like FINFET . At 45-nm Technology and beyond, new flow process adopted was High k + Metal Gate using Gate-Last strategy . In the future we hope to go from 45nm technology to 32nm technology to 22nm technology to 16nm technology. Today in Bipolar Technology we have achieved 200GHz transit frequency and in CMOS Technology quad core microprocessor has come in the market. Intel and AMD have launched a native quad processor using 45nm technology. Both achieve the 4 cores on the same silicon slab. This has Memory Bandwidth. These conserve energy by cutting down power when the device is idle. These four cores are built up of 40billion transistors.