9.3 Sspd_chapter 7_part 3_basic electrical properties of mos and  (Page 3/3)

L = length of the channel,

W = the width of the channel and D= thickness of the gate oxide.

We have to do the quantitative formulation of the n-channel charges induced in P-body after the Gate Voltage exceeds the threshold in case of (E)NMOS.

From now onward we will deal with (E)NMOS.

In (E)NMOS, positive gate voltage repels the majority carriers, namely holes, and creates depletion layer. In the process there is band-bending at the interface.

When band-bending = 2qψ _B then inversion layer is induced.

The charges on the two plates of the gate capacitance and the gate voltage is shown in Figure 7.3.11.

Q _g (the charge on the gate plate) = Q _dmax (depletion layer charge at its maximum width) + Q _i (inversion layer charge).

Q _i = inversion layer charge is the channel charge which we have referred to as the charge induced in the channel = Q _C

Q _C = D _g (electric flux density terminating at the induced channel charge) ×WL

--------------------------------------------------------------------------------------------------------7.3.9

Total electric flux originating = Q _g .

A part is terminating on (-ve)Q _dmax and the remaining is terminating on (-ve)Q _C . The part which is terminating on (-ve)Q _C is accounted by Eq.7.3.9.

But D _g = E _g ×ε _ins ×ε ₀

Where E _g = average gate electric field with respect to the channel,

ε _ins = relative permittivity of the gate oxide = 4 for Silicon Dioxide ,

ε ₀ = free space permittivity or absolute permittivity = 8.854×10 ^-14 F/cm.

To consider the average electric field (E _g ), we must consider the average electric field of the channel.

The Drain end of the channel is at V _ds and the source end is at 0V. Therefore the average voltage of the channel is (V _ds /2).

Also effective gate voltage responsible for induced channel charges or responsible for inversion layer is (V _gs – V _t ).

Hence average gate electric field with respect to the channel is:

Where D = oxide thickness.

Therefore:

Errata in equation 7.3.11

But

And

Substituting Eq.7.3.11 and Eq.7.3.8 in Eq.7.3.3 we get:

Gate Capacitance per unit area = C _ox and total gate Capacitance is C _g therefore

Equation 7.3.12 is also written as:

This equation is applicable in non-saturated region where

This non-saturated region is called ohmic region or triode region.

7.3.3.2. Output curves in Saturated Region (Pentode Region)

NMOS enters the saturated region when the trapezoidal channel pinches off from the drain side. This happens when

Equation 7.3.14 reduces to:

When V _ds exceeds V _ds ^* , still the voltage drop across the conical channel from the source to the apex of the cone remains V _ds ^* and the excess voltage (V _ds - V _ds ^* ) drops across the depleted region from the apex to the drain. By ballistic action electrons jump across the depleted region and maintain the current flow.

Equation 7.3.16 can be re-written as:

As is evident from Eq. 7.3.17, the line of demarcation between Triode and Pentode is a parabola which was pointed out in the the family of output curves in Figure 7.3.7.

These equations describing the output family of curves are valid for (E)NMOS as well as for (D)NMOS except that in (E)NMOS threshold is a positive voltage typically 1V and in (D)NMOS it is a negative voltage typically -1V. Equation 7.3.14 and Equation 7.3.16 show that the electrical characteristics are critically dependent on the geometrical dimensions of the MOS devices.