9.27 Sspd_chapter 7_part 7_scaling of mos circuits_continued2

SSPD_Chapter 7_Part 7_Scaling of MOS circuits_continued2

7.7.7. Scaling models and scaling factors.

In Figure 7.7.7.1. NMOS cross-secctional view and top view are shown.

Linear dimensions both vertical and lateral are being scaled by 1/α..

DC Biasing voltage ,V _DD , and Oxide thickness,D, are being scaled by 1/β.

We have three scaling models:

1. Constant Field Scaling Model- here physical dimensions and bias voltage have the same scaling factor therefore α = β;
2. Constant Voltage Scaling Model- here physical dimensions are scaled but bias voltage is kept constant therefore β = 1;
3. General Scaling Model- here the two scaling factors are kept different.This is more realistic and presently widely practiced in the Industries.

7.7.7.1.Scaling Factors for Device Geometrical parameters

1. Gate Area = A _g = L×W. Each dimension is scaled by 1/α hence A _g is scaled by 1/α ² .

2.Gate Capacitance per unit area = C _OX = ε ₀ ε _OX /D where D is scaled by 1/β therefore C _OX is scaled by β.

3. Gate Capacitance , C _g , = C _OX ×LW has a scaling factor of β/α ² .

4. Parasitic Capacitance, C _X = ε ₀ ε _Si A _X /d= junction capacitance of the diode at Source-Substrate Junction and at Drain-Substrate Junction. ‘d’ is the depletion width of the diode. Since Source and Drain are at 0V and 5V respectively and substrate is also at 0V therefore depletion region around Source and Drain are d1 and d2 respectively extending primarily into P-Substrate because the two diodes are one-sided step junctions There is a depletion region d3 under the gate in the substrate. This is due to the trapped charges in the gate-oxide and due to the positive voltage a the gate electrode.

In Figure 7.7.7.1 cross-sectional view of NMOS structure with depletion region of ‘d’μm width is illustrated in the upper figure and in the figure below ‘d’μm’ plot with respect to Background doping of P-substrate is shown.

From Device Physics we know that for one-sided step junction:

As the channel length is scaled down, depletion region width ‘d’ must also be scaled down to prevent the source and drain depletion regions from meeting. This is probably to prevent “Punch Through” - a phenomena which occurs in BJT also.

During scaling, cross-sectuional area A _X is scaled by 1/α ² and Backgound Doping is increased so that d is scaled by 1/α.

So the scaling factor of C _X is :

Increase in substrate doping N _B decreases ‘d’ but increases threshold voltage V _Th which is against the required trend of scaling and hence cannot be permitted therefore substrate doping is selectively increased around Source and Drain but not under the Gate by the application of deep channel implantation.

7.7.7.2.Scaling factors for different performance parameters for General Scaling Model.

i.Carrier density in the channel = Q _ON = C _OX ×V _GS . (since V _GS = V _DD hence scaling factor for V _GS is the same as for V _DD ). Hence scaling factor for Q _ON = β×(1/β) = 1

ii. Channel resistance R _ON is given as follows:

Where ρ is resistivity of the ON channel and σ is the conductivity of the ON channel and

Where μ _n = drift mobility of electrons since we are dealing with NMOS,

q= charge of an electron,

n _n = number density or electron number per unit volume of the channel therefore

Substituting Eq.7.7.2.2 and Eq 7.7.2.3 in Eq.7.7.2.1 we get:

Therefore From Eq.7.7.2.4: R _ON = (L/W)×[1/(μ _n Q _ON )]

Mobility is unaffected by scaling. Hence scaling factor is 1×1=1

iii Gate Delay τ _d = C _g R _ON = (L×W)C _OX ×(L/W)×[1/(μ _n Q _ON )] = L ² C _OX [1/(μ _n Q _ON )]

Therefore scaling factor of Gate Delay is (1/α ² )×β×1= β/α ² ;

iv Maximum toggle rate = f _max = 1/τ _d . Therefore the scaling factor is the reciprocal of that of Gate Delay i.e. (α ² /β) .

v Saturation Current I _DSS = (μ _n C _OX /2)(W/L)(V _GS -V _th ) ² Here both V _GS and V _th are being scaled by (1/β). Hence the scaling factor is β×1×(1/β) ² =1/β.

vi. Switching energy per gate E _gate = (1/2)C _g (V _DD ) ² . The scaling factor is (β/α ² )(1/β) ² =

1/(α ² β).

vii. Power dissipation per gate P _gate = Quiescent Power + Dynamic Power

= (V _DD ) ² /R _ON + f _max ×E _gate . Hence the scaling factor is (1/β) ² ×1+(α ² /β)×(1/(α ² β)

=1/β ² .

viii. Power dissipation per unit area = P _□ = P _gate /A _gate . Therefore the scaling factor = (1/β ² )/(1/α ² ) = (α/β) ² .

ix. Power Speed Product is the Figure of Merit of the Gate = P _gate × τ _d . This has a scaling factor = 1/β ² × β/α ² =1/(βα ² ).

Table 7.7.7.2.1. Scaling factors for different performance parameters for General Scaling Model.

7.7.7.3. Scaling factors for all the three scaling models.

In this section we will tabulate the scaling factors for all the three scaling models namely:

1. Constant Electric Field Model also known as Full Scaling Model. Here α=β.
2. Constant Voltage Model also known as Fixed Voltage Model. Here β =1.
3. General Scaling Model. Here two scaling factors are kept different. This is most realistic and generally accepted by Industries.

Table 7.7.7.3.1. Scaling Factors for long channel devices for the three scaling models.

*From Eq.7.7.7.1.1 :