8.8 Sspd_chapter 6_part 6_mos ics fabrication technology_to be  (Page 4/4)

The average range of penetration is R _P = this is the range below the surface of the wafer where maximum number of ions are implanted and this ion peak concentration is given by C _P .

The concentration at any range ‘x’ is given by:

The dose of implant is Q = √(2π)ΔR _P C _P 6.17

Here ΔR _P = the standard deviation or straggle about the average range R _P .

After the implantation the damage inflicted to the silicon surface is annealed at high temperature. By annealing the damage gets repaired. The dislodged Si atoms diffuse to a vacant lattice site and fills up the defect. The annealing cycle is carried out at 1000°C for 10 seconds or at 800°C for 30 minutes.

During the annealing process the ion implant diffuses out but maintains the Gaussian distribution as shown in Figure 6.43

During ion-implantation, a thick layer of photo-resist (1µm) is an effective mask for shielding the areas where implantation is not desired. This is because ion-implantation is carried out at room temperature.

Section 6.6.2.3 Active Region Formation.

In bipolar technology we did isolation diffusion for isolating the active devices. Here we grow field oxide to isolate the MOS devices. The field oxide is grown by a technique called LOCOS described in Section 6.4.3 and in case of ULSI circuits we use Poly buffered LOCOS as described in Section 6.4.5.

As already discussed in Section 6.4.3 LOCOS suffers from bird’s beak problem. To circumvent this problem we adopt Shallow Trench Isolation. Instead of growing Field Oxide , in place of Field Oxide we etch out a shallow 500nm deep trench in Silicon, then we grow a thin layer of Oxide and fill it up with Silicon Dioxide. The thin layer of oxide is grown on the bottom and side of the trench by thermal oxide. This step reduces the charges at the Si/SiO ₂ interface. This gives a vertical edge to the trench and removes the problem of bird’s beak which reduces the active area which cannot be afforded at VLSI/ULSI level. Next by CVD oxide is filled up in the trench and by Chemical Mechanical Polishing(CMP) planarization of the surface is done. This CMP process stops at Silicon Nitride.

The etchant of Silicon is Nitric Acid plus Hydrofluoric acid and the reaction is as follows:

Here the reaction takes place in two steps: Nitric Acid partially decomposes into NO ₂ and oxidizes Si and then HF acid etches SiO ₂ .

For defining the Field Oxide region or for defining the Shallow Trench, we use Mask Number 1.

The first step is:

Choosing a P type substrate of orientation<100>and resistivity of 15Ω-cm.

Second step is :

Thermal Oxidation for 15 minutes at 900°C in steam ambient or 45 minutes at 1000°C in dry O ₂ ambient. In either case we get 40nm Silicon Dioxide layer.

Third Step is:

Growing Silicon Nitride layer in a second oven at 800°C.

Fourth Step is:

We spin a Photo-Resist layer. Bake it at 100°C. Expose it through Mask 1. Develop it. Fix it so that the mask portion is resistant of the etchant. Next we do dry etching by Fluorine Plasma to etch out the Si ₃ N ₄ . In the masked region Si ₃ N ₄ is retained and elsewhere a window is made .

Fifth Step is:

Next fixed Photo-Resist layer is stripped by a stripper or stripped by Oxygen plasma.

Sixth Step is:

Next we do local oxidation (LOCOS) or shallow trench isolation(STI). The end result is shown in Figure 6.44 and Figure 6.45

Seventh Step :

By dry etching the remaining portion of Si3N4 layer is removed.

Eighth Step :

Mask 2 is used for retaining hardened KPR in PMOS and Boron is ion-implanted in NMOS region as shown in Figure 6.46. Implant dose will be 10 ¹³ per cm ² at an energy of 150 to 200keV. This will ensure a P-tub of 5×10 ¹⁶ to 10 ¹⁷ per cm ³ . By high temperature annealing the damage is healed. This may be 10sec at 1000°C or 30 min at 800°C. Hardened KPR is stripped by stripper or by Oxygen Plasma.

Ninth Step:

We use Mask 3 to implant the N-tub as shown in Figure 6.47. Phosphorous is almost 3 times heavier than Boron hence Phosphorous ions will be implanted at 300 to 400 keV. This will ensure the same kind of doping as in P-tub.

Tenth Step:

High temperature drive-in of P-tub and N-tub is done for 4 to 6 hours so as to drive the depth to 3 microns as shown in Figure 6.48.

There are several options for active regions and Tub formation. We will study only two options which are generally adopted in MOS fabrication technology. These are :

Option 1___Field implant. This provides a better isolation.

Option 2___Buried layer and Epitaxial layer. This minimizes the possibility of Latch-up through the parasitic BJTs.