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Again a thin layer of oxide is grown by 11 minutes dry oxidation at 925°C at a pressure of 1 atmosphere and HCl 3%.
The gate oxide is 20nm thick.
# Extract a design parameter
extract name="gateox" thickness oxide mat.occno=1 x.val=0.05
#
This statement extracts the gate-oxide thickness in the vertical section at xm = 0.05µm. The gate oxide thickness should be 11nm.
#vt adjust implant
implant boron dose=9.5e11 energy=10 pearson
To precisely control the threshold voltage in the range of 0.5V to 0.8V we do a second ion implantation.
Boron Implant Dose = 9.5×10 11 Boron ions/cm 2 and accelerating voltage is 10KeV and we invoke Dual Pearson Model.
The implant dose can be calculated from the formula:
V FB = flat band voltage;
Ψ F = (E i -E F )/q;
Q I = implanted dose;
C OX = ε oxide /t oxide ;
#
depo poly thick=0.2 divi=10
#
#from now on the situation is 2-D
#
etch poly left p1.x=0.35
#
Here we cover the P-Well with 0.2µm thick Poly_Si as shown in Figure 7.
This Poly_Si is etched left to x = 0.35µm as shown in Figure 8. The N Well is kept out of process simulation hence it is being shown as dotted structure.
method fermi compress
diffuse time=3 temp=900 weto2 press=1.0
#
Method Fermi Compress is invoked. We are using Fermi model which is applicable to structures having low damage and doping concentration below 1×10 20 dopents per cc.
3 minutes wet oxidation at 900°C is done at 1 atmosphere.
0.02µm oxide layer is obtained covering the entire surface as shown in Figure 9. It should be noted that this is wet oxidation and not conformal deposition. Hence Oxide layer is formed only in regions where Silicon is available. Necessity of this step is not clear.
implant phosphor dose=3.0e13 energy=20 pearson
#
Phosphorous implant of Dose 3×10 13 ions/cm 2 is carried out at an energy of 20KeV.
This phosphorous implant creates self-aligned LDD N-type Source as well as highly N-type doped Poly-Si Gate contact.
Side-Wall Spacer formation can be obtained as follows:
depo oxide thick=0.120 divisions=8
#
etch oxide dry thick=0.120
#
Here we deposit 0.12µm thick oxide and again etch the same amount. Because of conformal nature of deposition during the etching phase side-wall oxide is retained as shown in Figure 10.
Next we do Arsenic Ion-Implant in a larger dose:
implant arsenic dose=5.0e15 energy=50 pearson
#
Arsenic has very little diffusion coefficient hence during subsequent heat cycles it is not redistributed. Plus N + Source has to be formed hence Arsenic dose is larger and higher accelerating voltage is used to make implant range deeper. Compare this implant with LDD implant. The resulting structure is shown in Figure 11.
Now Metal contact has to be made to N+ source.
method fermi compress
diffuse time=1 temp=900 nitro press=1.0
#
Rapid annealing is done for 1 minute at 900°C
# pattern s/d contact metal
etch oxide left p1.x=0.2
deposit alumin thick=0.03 divi=2
Now Oxide is etched out left of the grid line xm=0.2µm.
Next Aluminum is deposited for Source Contact. The entire surface gets covered by Metal Layer shown in Black by conformal deposition method. As shown in Figure 12.
Next we etch out Metal(Al) from the entire surface except the Source contact which is made from xm = 0µm to xm = 0.18 µm. That is Source contact is 0.18µm long extending from the left edge to xm = 0.18 µm. Hence we give the command:
etch alumin right p1.x=0.18
The resulting structure is shown in Figure 13.
# Extract design parameters
# extract final S/D Xj
extract name="nxj" xj silicon mat.occno=1 x.val=0.1 junc.occno=1
# extract the N++ regions sheet resistance
extract name="n++ sheet rho" sheet.res material="Silicon" mat.occno=1 x.val=0.05 region.occno=1
# extract the sheet rho under the spacer, of the LDD region
extract name="ldd sheet rho" sheet.res material="Silicon" \
mat.occno=1 x.val=0.3 region.occno=1
# extract the surface conc under the channel.
extract name="chan surf conc" surf.conc impurity="Net Doping" \
material="Silicon" mat.occno=1 x.val=0.45
In the above statements following fabrication parameters are being extracted at the vertical sections of following physical locations of the MOS structure as shown in Figure 14.
At x.val = 0.05µm, Sheet Resistance of N++ Source region is to be extracted.
At x.val = 0.15µm, Junction depth of Source region is to be extracted.
At x.val = 0.3µm, Sheet Resistance of LDD is to be extracted.
At x.val = 0.05µm, Sheet Resistance of the channel below the gate-oxide is to be extracted.
# extract a curve of conductance versus bias.
extract start material="Polysilicon" mat.occno=1 \
bias=0.0 bias.step=0.2 bias.stop=2 x.val=0.45
extract done name="sheet cond v bias" \
curve(bias,1dn.conduct material="Silicon" mat.occno=1 region.occno=1)\
outfile="extract.dat"
Here the Gate Bias voltage is increased from 0V to 2V in step of 0.2V and sheet conductance versus Gate Bias Voltage curve is determined at the vertical section located at xm = 0.45µm.
# extract the long chan Vt
extract name="n1dvt" 1dvt ntype vb=0.0 qss=1e10 x.val=0.49
In this statement Threshold Voltage is extracted with bias voltage at 0V and Q SS = 1×10 10 at the vertical section situated at xm = 0.45µm.
structure mirror right
By this statement we are able to generate the whole (E)NMOS structure.
electrode name=gate x=0.5 y=0.1
electrode name=source x=0.1
electrode name=drain x=1.1
electrode name=substrate backside
structure outfile=mos1ex01_0.str
# plot the structure
tonyplot mos1ex01_0.str -set mos1ex01_0.set
############# Vt Test : Returns Vt, Beta and Theta ################
In the last four statements we are giving the name and location of the contact pads of the device generated.
We have Gate Contact Pad located at xm=0.5µm and ym = -0.1 µm;
Source Contact Pad at xm = 0.1 µm and on the surface of the device;
Drain Contact Pad at xm = 1.1 µm and on the surface of the device;
There is contact pad to the body at the backside.
Beta is the distribution function describing the dopent distribution.
Theta is the distribution function dealing with the interstitials.
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