8.3 Sspd_chapter 6_part 3_the challenges of ic technology  (Page 5/5)

The specific technology development challenges of a successful foundry company in the next decade include:______________________________________________________________

(1) aggressive scaling of transistors, interconnect, and design rules for both performance and density;____________________________________________________________________

(2) embedded technologies for SOC(System-on-Chip) solutions;_______________________

(3) cost effective and manufacturability process technology;___________________________

(4) a versatile technology portfolio;______________________________________________

and (5) easy integration among customers, design service/IP providers and the foundries.____

In the following years as the Foundries build their core competencies by including leading edge process technologies, advanced and flexible manufacturing capabilities and customer oriented service systems, the dichotomy between the Foundries and the Fab-less Companies will be complete.

As the scaling continues we need to answer the following challenges up to 90nm Generation Technology:

1. Sub-micron optical lithography(including Optical Proximity Corrections/Resolution Enhancement);
2. Extending bulk CMOS by several performance boosters- stress/strain, ultra shallow junctions and ox nitrides;
3. Multi-level Cu interconnects including Chemical Mechanical Polishing(CMP).

At 45nm Generation Technology and beyond the following challenges have to be

answered:

1. Device/process variability: In the micron Generation the yield loss was dominated by random defects in the wafer. By the time volume production started by suitable quality control of wafers, systematic yield losses was eliminated. But in sub-micron and deep submicron Generation Technology, random defect limited yield losses are less than 50%. Major losses come from lay-out systematics and parametric systematics. For 90nm NMOS Generation Technology, systematic variation in line width is 40% of the overall chip variance. The systematic variation in the line width has a serious effect on the electrical performance which in turn effects the yield. This layout systematics and parametric systematics have to be addressed by the circuit designer. The histogram in Figure 6.31 illustrates the above point.

1. Despite of new device architecture such as FinFET, Ultra-Thin Body Transistors(UTB), Inverted T FET, the bulk CMOS will dominate. With scaling, performance parameters become sensitive to random dopant fluctuations. Circuit designers will have to cope with much higher variability in parameters as well as higher leakage currents.
2. With scaling due to Fermi-Level pinning (AppendixIV), higher threshold Voltage (V _Thres ) resulted. Also High-k material have high elasticity hence result in higher phonon scattering or lattice scattering resulting in lower channel mobility. By screening the phonon effect, the deterioration in channel conductivity could be prevented. This required increasing the electron density in Poly-Si gate. Hence we had to switch to Metal-High k combination. This prevented:

1. Fermi-Level pinning hence threshold voltage normalized;
2. This normalized channel conductivity which had drastically deteriorated due to dipole vibration effect;
3. Metal Gate Electrode provides better bonding between Metal-Dielectric. Hence stable operation.

In mid-2003, Intel’s Hillsbaro, Ore, Development Fab developed HK-MG CMOS. Intel’s 130nm technology was used. Using Hafnium-Based Oxide and Metal Gate electrode following characteristics were achieved:

1. Low Threshold = 1V;
2. Negligible leakage current through Oxide;
3. High 2-D channel mobility.
4. Advanced Process Control(APC) especially feed forward: Given the increasing complexity and small process windows, yield variability is a very significant problem. New approaches for yield relevant SOC(System on Chip) and APC are needed to take advantage of the increased process observables due to in-situ equipment sensor/FDC deployment.
5. Compact device models: Below 100 nm, compact device models must accommodate microscopic (i.e., "non-bulk") physical effects with minimal impact on overall computational complexities.   BSIM has filled this role for many technology generations as the workhorse, both for model characterization and node-to-node technology predictions.  It continues to have the confidence of industry and seems likely to remain in service (with the possible exception of RF) down to about 45 nm. 

Compact models at 65 nm need to be urgently improved on account of the following:

(a) scalability of sub-threshold currents and output resistance from short-to-long channel lengths, due largely to lateral doping non-uniformities 

(b) dependence of noise on voltage and geometry; i.e., considering 1/f noise dependence on random noise trap occurrences

(c) capabilities for handling geometrical statistical fluctuations which affect noise, threshold voltage and drive current.

1. The above problems become more severe at 45 nm, along with the following additional priorities:

(1)  gate current scaling and dependences on novel (e.g., multi-layer) gate stacks,

(2)  carrier mobility in the channel due to layout-induced stress/strain,

(3)  statistical variations stemming from random dopant placements,

(4)  ballistic transport of carriers in intrinsic channel and, 

(5)  quantum mechanical effects due to confinement in thin films.

In nutshell, Scaling theory has been the organizing principle of the progress of the semiconductor industry throughout three decades. It has created a framework for continued improvement in density and cost performance and facilitated the desegregation of the entire industry around design and manufacturing. Few concepts in our time have had as much influence on the economy.

In this section we have done a rapid review of the challenges which have confronted the continuous microminiaturization of IC chips. In the next few sections we will study the specific technological developments and innovations made to meet these challenges.