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Using the MSP-EXP430FG4618 Development Tool and the MSP430FG4618 device implement a Memory Clock with Timer_A.

Laboratory timers: lab3 - memory clock with timer_a

Introduction

Correct system timing is a fundamental requirement for the proper operation of a real-time application. The timing definition can dictate how the data information processed during the execution of the application program. The clock implementations vary between devices in the MSP430 family. Each device provides different clock sources, controls and uses. This chapter discusses the clock controls included in the platforms used. The MSP430 4xx family has two general-purpose 16-bit or 8-bit counters and event timers, named Timer_A, Timer_B, and a Basic Timer. The Basic Timer module is only implemented in ‘4xx devices. The 2xx device family also has Timer_A and Timer_B, but the clock signals are provided by the basic clock module+.The timers may receive an internal or external clock. Timer_A and Timer_B also include multiple independent capture and compare blocks, with interrupt capabilities.

Overview

The objective of this laboratory is to build a memory clock similar to the one that was developed using the Basic Timer1, in laboratory Timers: Lab1 - Memory clock with Basic Timer1 . Timer_A is configured to generate an interrupt once every 100 msec. The ISR manages the memory clock. LED1 and LED2 are used to monitor the operation of the system state.

Resources

This application ( Lab3_Timers.c ) makes use of Timer_A to generate an interrupt when the value in the TACCR0 unit is reached. The ISR updates the contents of the memory clock variables.

LED1 monitors the system operation, switching state whenever the Timer_A ISR runs. LED2 can be used to monitor the ISR execution time. The contents of the LCD is updated every interrupt. When the ISR finishes, the device returns to low power mode.

Hence, the system resources used by this application are:

- Timer_A;

- I/O ports;

- LCD;

- Interrupts;

- Low power modes.

The default configuration of the FLL+ is used, so all the clock signals required for the operation of the device assume their default values.

Software application organization

The first task is to disable the Watchdog Timer. All the resources needed for the LCD are then configured. Once configured, the LCD is cleared by the execution of the routine LCD_all_off() .

The memory clock consists of three global variables: min , sec , msec , of the type unsigned char , to store the minutes, seconds and milliseconds respectively of the values elapsed since the beginning of the execution of the application. These variables are initialized with zeros.

The LCD is refreshed at startup to display the initial clock value.

LED2 is used as an indicator of Timer_A ISR execution. The execution time can be monitored using it. In addition, LED1 switches state whenever Timer_A ISR is executed.

Timer_A is configured to generate an interrupt once every 100 milliseconds.

The routine main() ends with a global interrupt enable and puts the device into a low power mode, where it waits for the next interrupt.

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Source:  OpenStax, Teaching and classroom laboratories based on the “ez430” and "experimenter's board" msp430 microcontroller platforms and code composer essentials. OpenStax CNX. May 19, 2009 Download for free at http://cnx.org/content/col10706/1.3
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