The phase lock loop provides estimates of the phase of the
incoming modulated signal. A phase ambiguity of exactly
$\pi $ is a common occurance in many phase
lock loop (PLL) implementations.
Therefore it is possible that,
$\widehat{\theta}=\theta +\pi $ without the knowledge of the receiver. Even if there is no noise, if
$b=1$ then
$\widehat{b}=0$ and if
$b=0$ then
$\widehat{b}=1$ .
In the presence of noise, an incorrect decision due to noise may
results in a correct final desicion (in binary case, when thereis
$\pi $ phase ambiguity with the
probability:
$\overline{{P}_{e}}=1-Q(\sqrt{\frac{2{E}_{s}}{{N}_{0}}})$
Consider a stream of bits
${a}_{n}\in \{0, 1\}$ and BPSK modulated signal
$\sum_{n} -1^{{a}_{n}}A{P}_{T}(t-nT)\cos (2\pi {f}_{c}t+\theta )$
In differential PSK, the transmitted bits are first encoded
${b}_{n}={a}_{n}\mathop{\mathrm{xor}}{b}_{n-1}$ with initial symbol (
e.g.
${b}_{0}$ ) chosen without loss of generality to be either 0 or 1.
Transmitted DPSK signals
$\sum_{n} -1^{{b}_{n}}A{P}_{T}(t-nT)\cos (2\pi {f}_{c}t+\theta )$
The decoder can be constructed as
${b}_{n-1}\mathop{\mathrm{xor}}{b}_{n}={b}_{n-1}\mathop{\mathrm{xor}}{a}_{n}\mathop{\mathrm{xor}}{b}_{n-1}=0\mathop{\mathrm{xor}}{a}_{n}={a}_{n}$
If two consecutive bits are detected correctly, if
${\widehat{b}}_{n}={b}_{n}$ and
${\widehat{b}}_{n-1}={b}_{n-1}$ then
${\widehat{a}}_{n}={\widehat{b}}_{n}\mathop{\mathrm{xor}}{\widehat{b}}_{n-1}={b}_{n}\mathop{\mathrm{xor}}{b}_{n-1}={a}_{n}\mathop{\mathrm{xor}}{b}_{n-1}\mathop{\mathrm{xor}}{b}_{n-1}={a}_{n}$
if
${\widehat{b}}_{n}={b}_{n}\mathop{\mathrm{xor}}1$ and
${\widehat{b}}_{n-1}={b}_{n-1}\mathop{\mathrm{xor}}1$ . That is, two consecutive bits are detected
incorrectly. Then,
${\widehat{a}}_{n}={\widehat{b}}_{n}\mathop{\mathrm{xor}}{\widehat{b}}_{n-1}={b}_{n}\mathop{\mathrm{xor}}1\mathop{\mathrm{xor}}{b}_{n-1}\mathop{\mathrm{xor}}1={b}_{n}\mathop{\mathrm{xor}}{b}_{n-1}\mathop{\mathrm{xor}}1\mathop{\mathrm{xor}}1={b}_{n}\mathop{\mathrm{xor}}{b}_{n-1}\mathop{\mathrm{xor}}0={b}_{n}\mathop{\mathrm{xor}}{b}_{n-1}={a}_{n}$
If
${\widehat{b}}_{n}={b}_{n}\mathop{\mathrm{xor}}1$ and
${\widehat{b}}_{n-1}={b}_{n-1}$ , that is, one of two consecutive bits is detected in
error. In this case there will be an error and the probabilityof that error for DPSK is
${\overline{P}}_{e}=({\widehat{a}}_{n}\neq {a}_{n})=({\widehat{b}}_{n}={b}_{n}, {\widehat{b}}_{n-1}\neq {b}_{n-1})+({\widehat{b}}_{n}\neq {b}_{n}, {\widehat{b}}_{n-1}={b}_{n-1})=2Q(\sqrt{\frac{2{E}_{s}}{{N}_{0}}})$
2
Q
2
E
s
N
0 This approximation holds if
$Q$ is
small.