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Addressing modes
The MSP430 supports seven addressing modes for the source operand and four addressing modes for the destination operand (see bellow). The following sections describe each of the addressing modes, with a brief description, an example and the number of CPU clock cycles required for an instruction, depending on the instruction format and the addressing modes used.
| Mode | Source operand | Destination operand | Description |
| Register mode | X | X | Single cycle |
| Indexed mode | X | X | Table processing |
| Symbolic mode | X | X | Easy to read code, PC relative |
| Absolute mode | X | X | Directly access any memory location |
| Indirect register mode | X | Access memory with pointers | |
| Indirect auto increment mode | X | Table processing | |
| Immediate mode | X | Unrestricted constant values |
Before describing the addressing modes, it is important to mention the clock cycles required by interrupts and resets.
| Action | Cycles | Length (words) |
| Return from interrupt | 5 | 1 |
| Interrupt accepted | 6 | - |
| Watchdog timer reset | 4 | - |
| Hard reset | 4 | - |
Register mode operations work directly on the processor registers, R4 through R15, or on special function registers, such as the program counter or status register. They are very efficient in terms of both instruction speed and code space.
Description: Register contents are operands.
Source mode bits: As = 00 (source register defined in the opcode).
Destination mode bit: Ad=0 (destination register defined in the opcode).
Syntax: Rn.
Length: One or two words.
Comment: Valid for source and destination.
Example 1: Move (copy) the contents of source (register R4) to destination (register R5). Register R4 is not affected.
Before operation: R4=A002h R5=F50Ah PC = PC pos
Operation: MOV R4, R5
After operation: R4=A002h R5=A002h PC = PC pos + 2
The first operand is in register mode and depending on the second operand mode, the cycles required to complete an instruction will differ. The next table shows the cycles required to complete an instruction, depending on the second operand mode.
| Operands | 2 nd operand mode | Operator | Cycles | Length (words) |
| 2 | Register | Any | 1* | 1 |
| 2 | Indexed, Symbolic or Absolute | Any | 4 | 2 |
| 1 | N/A | RRA, RRC, SWPB or SXT | 1 | 1 |
| 1 | N/A | PUSH | 3 | 1 |
| 1 | N/A | CALL | 4 | 1 |
The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn is one of the CPU registers. The absolute memory location X+Rn is addressed. Indexed mode addressing is useful for applications such as lookup tables.
Description: (Rn + X) points to the operand. X is stored in the next word.
Source mode bits: As = 01 (memory location is defined by the word immediately following the opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the opcode).
Syntax: X(Rn).
Length: Two or three words.
Comment: Valid for source and destination.
Example 2: Move (copy) the contents at source address (F000h + R5) to destination (register R4).
Before operation: R4=A002h R5=050Ah Loc:0xF50A=0123h
Operation: MOV F000h(R5), R4
After operation: R4=0123h R5=050Ah Loc:0xF50A=0123h
| Operands | 2 nd operand mode | Operator | Cycles | Length (words) |
| 2 | Register | Any | 3 | 2 |
| 2 | Indexed, Symbolic or Absolute | Any | 6 | 3 |
| 1 | N/A | RRA, RRC, SWPB or SXT | 4 | 2 |
| 1 | N/A | CALL or PUSH | 5 | 2 |
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