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Parallel instructions and constraints

We have seen that C62x CPU has 8 functional units. Each assembly instruction is executed in one of these 8 functionalunits, and it takes exactly one clock cycle for the execution. Then, while one instruction is being executed inone of the functional units, what are other 7 functional units doing? Can other functional units execute other instructionsat the same time?

The answer is YES. Thus, the CPU can execute maximum 8 instructions in each clock cycle. The instructions executedin the same clock cycle are called parallel instructions . Then, what instructions can be executed in parallel? A short answer is: as far as the parallelinstructions do not use the same resource of the CPU, they can be put in parallel. For example, the following twoinstructions do not use the same CPU resource and they can be executed in parallel.

1 ADD .L1 A0,A1,A2 2 || ADD .L2 B0,B1,B2

Resource constraints

Then, what are the constraints on the parallel instructions? Let's look at the resource constraints in more detail.

Functional unit constraints

This is simple. Each functional unit can execute only one instruction per each clock cycle. In other words,instructions using the same functional unit cannot be put in parallel.

Cross paths constraints

If you look at the data path diagram of the C62x CPU, there exists only one cross path from B register file to the L1 , M1 and S1 functional units. This means the cross path can be used only once per each clock cycle.Thus, the following parallel instructions are invalid because the 1x cross path is used for both instructions.

1 ADD .L1x A0,B1,A22 || MPY .M1x A5,B0,A3

The same rule holds for the 2x cross path from the A register file to the L2 , M2 and S2 functional units.

Loads and stores constraints

The D units are used for load and store instructions. If you examine the C62x data pathdiagram, the addresses for load/store can be obtained from either A or B side using the multiplexers connectingcrisscross to generate the addresses DA1 and DA2 . Thus, the instructions such as

1 LDW .D2 *B0, A1

is valid. The functional unit must be on the same side as the address source register (address index in B0 and therefore D2 above), because D1 and D2 units must receive the addresses from A and B sides,respectively.

Another constraint is that while loading a register in one register file from memory, you cannot simultaneously storea register in the same register file to memory. For example, the following parallel instructions are invalid:

1 LDW .D1 *A0, A1 2 || STW .D2 A2, *B0

Constraints on register reads

You cannot have more than four reads from the same register in each clock cycle. Thus, thefollowing is invalid:

1 ADD .L1 A1, A1, A2 2 || MPY .M1 A1, A1, A33 || SUB .D1 A1, A4, A5

Constraints on register writes

A register cannot be written to more than once in a single clock cycle. However, note that the actual writing toregisters may not occur in the same clock cycle during which the instruction is executed. For example, the MPY instruction writes to the destination register in the next clock cycle. Thus, thefollowing is valid:

1 ADD .L1 A1, A1, A2 2 || MPY .M1 A1, A1, A2

The following two instructions (not parallel) are invalid (why?):

1 MPY .M1 A1, A1, A2 2 ADD .L1 A3, A4, A2

Some of these write conflicts are very hard to detect and not detected by the assembler. Extra caution should beexercised with the instructions having nonzero delay slots.

Ad-hoc software pipelining

At this point, you might have wondered why the C62x CPU allows parallel instructions and generate so much headachewith the resource constraints, especially with the instructions with delay slots. And, why not just make the MPY instruction take 2 clock cycles to execute so that we can always use the multiplied resultafter issuing it?

The reason is that by executing instructions in parallel, we can reduce the total execution time of the program. Awell-written assembly program executes as many instructions as possible in each clock cycle to implement the desiredalgorithm.

The reason for allowing delay slots is that although it takes 2 clock cycles for an MPY instruction generate the result, we can execute another instruction while waiting for the result. This way, you canreduce the clock cycles wasted while waiting for the result from slow instructions, thus increasing the overallexecution speed.

However, how can we put instructions in parallel? Although there's a systematic way of doing it (we will learn a bitlater), at this point you can try to restructure your assembly code to execute as many instructions as possible inparallel. And, you should try to execute other instructions in the delay slots of those instructions such as MPY , LDW , etc. , instead of inserting NOP s to wait the instructions produce the results.

(parallel instructions): Modify your assembly program for the inner product computation in the previousexercise to use parallel instructions as much as possible. Also, try to fill the delay slots as much aspossible. Using the code composer's profiling, compare the clock cycles necessary for executing the modifiedprogram. How many clock cycles could you save?

Intentionally left blank.

Questions & Answers

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Source:  OpenStax, Finite impulse response. OpenStax CNX. Feb 16, 2004 Download for free at http://cnx.org/content/col10226/1.1
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