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Suppose that our design objective is to build a digital processor capable of demodulating all of the FSK canals found in the R.35 signal shown in Figure 1 from "An Introduction to the FDM-TDM Digital Transmultiplexer: Introduction" . Suppose further that we choose to build the demodulator for each FSK signal along the lines of the one shown Note that this demodulator design is slightly different than the one discussed in the section "What is an FDM-TDM Transmultiplexer" . in [link] (a). Both are used in practice. This type of FSK demodulator uses two fllters: one centered at the mark frequency f m k and another the space frequency f s p . The powers or amplitudes of the two filter outputs are compared to determine whether the signal instantaneously falls mostly in the vicinity of the mark or is closer to the space. The bit synchronizer logic monitors the transitions between mark and space (and vice versa), using the information to determine the right instants to sample the thresholded difference waveform and produce binary decisions.

[link] shows the block diagram of the demodulating process when extended to handle all 24 FSK canals in an R.35 signal. Initially it appears to only be 24 parallel demodulators. On closer inspection however, it may be recognized that the center frequencies of all the filters differ by integer multiples of a single frequency increment Δ f . This suggests the use of a digital filter bank to compute all ofthe required bandpass filters. We now proceed to see how the system design for this filter bank is done.

The system design of the transmultiplexer/filter bank is specified by a small set of parameters. We determine these parameters as follows:

  • Δ f : Inspection of the frequency allocations for the R.35 signal shows that all possible mark and space frequencies are separated by integer multiples of 60 Hz. Thus it is natural to set Δ f = 60 Hz.
  • f s and N : With Δ f determined, the choice of N , the DFT dimension, and the choice of the input sampling rate f s , are locked together. We bound N from below, by noting that at least 48 filters are needed, two for each FSK canal. In principle, the value of N can be chosen to be any number higher than 48. If the use of the FFT is contemplated then N is usually chosen to the first power of 2 or 4 higher than the minimum value [link] introduces some additional considerations in the design of digital systems in which the transmultiplexer is only a part. . Assuming the use of either a radix-2 or radix-4 FFT, plus the use of complex-valued input data, the prudent value of N is 64. This immediately leads to a complex-valued input sampling rate of N · Δ f = 3840 Hz. If the input were real-valued instead, then the chosen sampling rate would be twice that, or 7680 Hz.
    Figure one is comprised of two flow charts. Part a is titled FSK Demodulator Employing Bandpass Filters Centered at the Mark and Space Frequencies. It begins on the left side with the caption, Input FSK signal. Below and to the side are a series of waves on an arbitrary horizontal line, labeled f_sp, f_mk, f_sp, f_mk. From the first caption, a line extends up and down, then to the right towards two rectangles. The upper rectangle is titled Bandpass Filter Centered @f_sp. The lower rectangle is titled Bandpass Filter Centered @f_mk. Above the upper rectangle is a small graph of two waves that begin and end along a horizontal axis, labeled f, and have peaks and the labeled points f_m on the left and f_s on the right. Both rectangles continue with an arrow pointing to the right at two more rectangles containing the caption |⋅|. After this are two arrows from these rectangles both pointing at the same circle in the middle, containing a large plus sign. The arrow from the upper row of rectangles is labeled with a +, and the arrow from the bottom row is labeled with a -. To the right of the circle is a line pointing at another rectangle, containing a large f-shaped line intersection. In the middle of this connecting line to the rectangle is an arrow pointing downward at another rectangle titled Bit Sync. This rectangle is followed by another arrow pointing back up towards the rectangle containing the f-shape, with the arrow labeled {. . 1, 0, 1, 0, . . .}. To the right of the f-shaped rectangle is one arrow pointing directly to the right, labeled {1 0}, and one pointing up and to the right, labeled Binary Decisions. Above both rectangles is a graph containing a wavering graph about a horizontal axis, with the positive portion of the graph labeled f_sp, and the lower portion labeled f_mk. Part b is titled Extension to an FDM FSK VFT Signal by Using a Transmultiplexer to Perform the Required Bandpass Filtering. The left side begins with the title Input FDM VFT Signals Carrying N FSK Canals. This caption is followed by a flowchart that spreads out to six rows. These rows begin with rectangles that read from top to bottom, BPF @ f_mk, 1 = f_b, BPF @ f_sp, 1 = f_b + ∆f, BPF @ f+mk, 2 = f_b + 2 ⋅ ∆f, BPF @ f_sp, 2 = f_b + 3 ⋅ ∆f, BPF @ f_mk, N = f_b + (2N-2) ⋅ ∆f, BPF @ f_sp, N = f_b + (2N-1) ⋅ ∆f. In between the fourth and fifth rectangles are a series of vertical dots indicating a continuing series. To the right of these rectangles aligned in their rows are six more rectangles each containing the caption |⋅|. In groups of two, the adjacent rectangle rows meet together at a circle containing a +. The arrows leading to this circle from the rectangles are labeled + above and - below. To the right of these circles are three rectangles labeled Bit Sync and Slice. To the right of these are arrows pointing to the right at captions that read from top to bottom, Binary Output for Canal 1, Binary Output for Canal 2, and Binary Output for Canal N.
    A Basic Two-Filter FSK Demodulator and its Filter Bank Extension
  • L and Q : Wth N determined, we find that L and Q are locked together and that they are a function of the exact filter design used to select the pulse response (or, equivalently, the window function) used to determine the shape of the bandpass fllters. The issues to be considered in the design of the pulse response are discussed in "An Introduction to the FDM-TDM Digital Transmultiplexer: Appendix A" . Without reiterating them here, we observe that following those rules yields a minimum pulse response duration L of about 174. For this application we extend the filter pulse duration to 192, allowing Q to equal exactly 3.
  • M : With the input sampling rate set, the decimation factor M determines the output sampling rate at each of the filter outputs. Thus f o u t , the output sampling rate, equals 3840 M Hz. The required output rate depends on the types of signals present and the types of processing to be done to them. In the case of demodulating asynchronous FSK signals, experience has shown that the output sampling rate needs to exceed the highest FSK baud rate expected by a factor of four or more. The highest baud rate allowed by the CCITT for an R.35 canal is 75 Hz The other rates are 50 and 60 Hz. . Thus the output sampling rate f o u t must exceed 300 Hz. By choosing M = 12 , we obtain an output sampling rate of f o u t = 320 Hz.

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Source:  OpenStax, An introduction to the fdm-tdm digital transmultiplexer. OpenStax CNX. Nov 16, 2010 Download for free at http://cnx.org/content/col11165/1.2
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