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Chapter 5 , Part 3 describes the VHDL Synthesis of Electric Motor Rotation Sensor.This SENSOR gives GREEN LED output for Clockwise sense of rotation and RED LED output for anti-Clockwise sense of rotation.

DSD_Chapter 5_StateMachines_Part2_MooreMachineDesign

5.5 Designing and implementing Motor Rotation Sensor.

The customer wants a Motor Rotation Sensor. The sensor should indicate if the Motor is spinning in Anti-Clockwise (Negative) or Clockwise (Positive) direction.

Figure 1.Schematic Diagram of the Architecture of Rotation Sensing Machine.

As can seen from Figure 1 there are two Sensors 1 and 2 which are so spatially placed that they generate a square wave with 90 degree phase shift corresponding to P1 and P2. When both are ‘00’ then Negative Rotation changes this to ‘01’ and Positive Rotation changes this to ‘10’.

We will take Moore Machine Design approach. Figure 2 gives the state diagram:

Figure 2. State Diagrams ofRotation Sensing Machine.

As shown in Figure 3 , the state code is sampled and stored in the REGISTER at the lagging/leading edge of the clock pulse. The state code in the Register decides the output. Since there are four distinct STATES hence there are four distinct OUTPUTS. So we have two-bit CODE {a0 , a1} to define the four states and we have two-bit std_logic_vector output “b0b1” to define the four corresponding outputs.

The two-bit std_logic_vector input “P1P2” are obtained from the sensors mounted over the encoding disc which in turn is mounted on the axle of the rotating motor. The Clock of the REGISTER must be synchronized with the motor speed so that all the four states are continuously monitored by the REGISTER.

If S2 state follows S1 then we have LED1 lit up which signifies that negative rotation of the motor and if S3 follows S1 then LED2 lights up signifying positive rotation.

Figure 3. Architecture of Moore Type Rotation Sensor.

In VHDL representation the Moore Sensor is as follows:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity MooreMachine_Rot_Sens is

___Port ( clk : in STD_LOGIC;

______in1 : in STD_LOGIC_VECTOR(1 downto 0);

______reset : in STD_LOGIC;

______out1 : out STD_LOGIC_VECTOR(1 downto 0));

end MooreMachine_Rot_Sens;

architecture Behavioral of MooreMachine_Rot_Sens is

type state_type is (s0,s1,s2,s3);----State declaration

signal state:state_type;

begin

process(clk,reset)---clocked process

begin

______if reset= '1' then

____________state<= s0;--------reset state

______elsif clk'event and clk= '1' then

____________case state is

____________when s0=>

__________________if in1 = "00" then

_______________________state<=s1;

_________________end if;

____________when s1=>

__________________if in1 = "10" then

________________________state<=s2;

__________________elsif in1 = "01" then

________________________state<=s3;

__________________elsif in1 = "11" then

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Source:  OpenStax, Digital system design using vhdl. OpenStax CNX. Apr 01, 2013 Download for free at http://cnx.org/content/col11213/1.8
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