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Other vector lengths

If V L > 1 , the list of nodes that results from the elaborate function in [link] is vectorized. Broadly speaking, CNodeLoad objects that operate on adjacent memory locations are collected together and computed in parallel. After each such computation, each position in a vector register contains an element that belongs to a different node. Transposes are then used to transform sets of vector registers such that each register contains elements from one node. Finally, the CNodeBfly objects can be easily computed in parallel, as they were with VL-1 because the elements in each vector register correspond to one node.

Overview

[link] lists the nodes that represent a VL-1 size-16 transform. A VL of 2 implies that each vector register contains 2 complex words, and load operations on each of the 4 addresses in the first row of [link] will also load the complex words in the adjacent memory locations. Note that the complex words that would be incidentally loaded in the upper half of the VL-2 registers are the complex words that the third CNodeLoad object at row 5 would have loaded. This is exploited to load and compute the first and third CNodeLoad objects in parallel.

VL-1 size-16 conjugate-pair transform nodes
Type Size Addresses Registers Twiddle
CNodeLoad 4 {0,8,4,12} {0,1,2,3}
CNodeLoad 2(x2) {2,10,14,6} {4,5,6,7}
CNodeBfly 4 {0,2,4,6} ω 16 0
CNodeBfly 4 {1,3,5,7} ω 16 2
CNodeLoad 4 {1,9,5,13} {8,9,10,11}
CNodeLoad 4 {15,7,3,11} {12,13,14,15}
CNodeBfly 4 {0,4,8,12} ω 16 0
CNodeBfly 4 {1,5,9,13} ω 16 1
CNodeBfly 4 {2,6,10,14} ω 16 2
CNodeBfly 4 {3,7,11,15} ω 16 3
VL-2 size-16 conjugate-pair transform nodes
Type Sizes Addresses Registers Twiddles
Load {4,4} {{0,1},{8,9},{4,5},{12,13}} {{0,1},{2,3},{8,9},{10,11}}
Load {2(x2),4} {{2,3},{10,11},{14,15},{6,7}} {{4,5},{6,7},{14,15},{12,13}}
Bfly {4,4} {{0,1},{2,3},{4,5},{6,7}} { ω 16 0 , ω 16 2 }
Bfly {4,4} {{0,1},{4,5},{8,9},{12,13}} { ω 16 0 , ω 16 1 }
Bfly {4,4} {{2,3},{6,7},{10,11},{14,15}} { ω 16 2 , ω 16 3 }

The second CNodeLoad object computes two size-2 leaf transforms in parallel, while the last CNodeLoad object computes a size-4 leaf transform. Because the size-4 transform is composed of two size-2 transforms, and memory addresses of the fourth CNodeLoad are adjacent (although permuted), some of the computation can be computed in parallel.

If the CNodeLoad objects at rows 1 and 5 are computed in parallel, the output will be four VL-2 registers: {{0,8}, {1,9}, {2,10}, {3,11}} – i.e., the first register contains what would have been register 0 in the lower half, and what would have been register 8 in the top half etc. Similarly, computing rows 2 and 6 in parallel would yield four VL-2 registers: {{4,14}, {5,15}, {6,12}, {7,13}} – note the permutation of the upper halves in this case. These registers are transposed to {{0,1}, {2,3}, {8,9}, {10,11}} and {{4,5}, {6,7}, {14,15}, {12,13}}, as in row 1 and 2 of [link] .

With the transposed VL-2 registers, it is now possible to compute CNodeBfly nodes in parallel. For example, rows 2 and 3 of [link] can be computed in parallel on four VL-2 registers represented by {{0,1}, {2,3}, {4,5}, {6,7}}, as in row 3 of [link] .

Implementation

[link] is a C++ implementation of the vectorize_loads function. This function modifies a topological ordering of nodes (the class member variable ns ) and uses two other functions: find_parallel_loads , which searches forward from the current node to find another CNodeLoad that shares adjacent memory addresses; and merge_loads(a,b) , which adds the addresses, registers and type of b to a . Type introspection is used at lines 7 and 36 (and in other Listings), to differentiate between the two types of object.

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Source:  OpenStax, Computing the fast fourier transform on simd microprocessors. OpenStax CNX. Jul 15, 2012 Download for free at http://cnx.org/content/col11438/1.2
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