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System configuration

Adc12 configuration:

The ADC12 module is configured in order to have the following characteristics:

- Single-channel, single-conversion operation;

- Uses the internal signal V REF+ (2.5 V) as reference voltage;

- The sample-and-hold time must be 64 ADC12CLK cycles;

- The conversion result must be available on ADC12MEM0;

- The sample-and-hold clock source is defined by software.

ADC12CTL0 |= SHT02|REF2_5V|REFON|ADC12ON|ENC|ADC12SC; //SHT1x (Sample-and-hold time) = 0000b ->N/A //SHT0x (Sample-and-hold time) = 0010b ->64 ADC12CLK //MSC (Multiple sample and conversion) = 0b ->N/A //REF2_5V (Reference generator voltage) = 1b ->2.5 V //REFON (Reference generator on) = 1b ->Reference on //ADC12ON (ADC12 on) = 1b ->ADC12 on //ADC12OVIE (overflow-int. enable) = 0b ->disabled //ADC12TOVIE (conversion-time-overflow int enable) = 0b// ->disabled //ENC (Enable conversion) = 0b ->enable configuration //ADC12SC (Start conversion) = 1b ->Start conversion ADC12CTL1 = CSTARTADD_0; // Start MEM0, TB1, Rpt Sing.//CSTARTADDx (Conv. start address.) = 0000b ->ADC12MEM0 //SHSx (Sample-and-hold source) = 00b ->ADC12SC bit //SHP (Sample-and-hold pulse-mode select) = 0b// ->SAMPCON is sourced from the sample-input signal //ISSH (Invert signal S-H) = 0b ->not inverted //ADC12DIVx (ADC12 clock divider) = 000b ->/1 //ADC12SSELx (ADC12 clock source) = 00b ->ADC12OSC //CONSEQx (Conversion sequence mode) = 00b ->Single- // channel, single-conversion//ADC12BUSY (ADC12 busy) = xb ->read only

The ADC12 module operates with reference voltages: V R+ = V REF+ and V R - = AV SS . The channel selected to perform the analogue-to-digital conversion is channel A1. This channel is internally connected the OA0’s output.

ADC12MCTL0 = INCH_1 | SREF_1; //EOS (End of sequence) = 0b ->Not Used //SREFx (Select ref.) = 001b ->VR+=VREF+/VR-=AVSS //INCHx (Input channel select) = 0001b ->A1

Dac12 configuration:

DAC12_0DAT = 0x00; // DAC_0 output 0VDAC12_0CTL = DAC12IR | DAC12AMP_5 | DAC12ENC; //DAC_0 ->P6.6 //DAC_1 ->P6.7 //DAC reference Vref//12 bits resolution //Immediate load//DAC full scale output //Medium speed///Straight binary //Not grouped

Oa0 configuration

The OA module of the MSP430FG4168 has three operational amplifiers with wide utilization flexibility. For this laboratory it is set up using the OA0 in non-Inverting PGA mode with the following configuration:

- The inverting input is connected to the DAC12 channel 0;

- The amplifier gain is configured as unity;

- The input is configured in rail-to-rail mode;

- The output is connected to the channel A1.

OA0CTL1 |= OAFC_4 | OAFBR_0; //OAFBRx (feedback resistor) = 000b ->Tap 0 (G=1) //OAFCx (OAx function) = 100b ->Non-inverting PGA //OARRIP = 0b ->OAx input range is rail-to-rail OA0CTL0 |= OAP_2 | OAPM_3 | OAADC1;//OANx (Inverting input) = XXb ->not important //OAPx (Non-inverting input) = 10b ->DAC0 internal //OAPMx (Slew rate select) = 11b ->Fast //OAADC1 (OA output) = 1b ->output connected to A1 //OAADC0 (OA output) = 0b ->output not connected A12

Adc12 isr

#pragma vector=ADC12_VECTOR __interrupt void ADC_ISR(void){ int x;x = ADC12MEM0; // Reads data ADC12CTL0 |= ADC12SC; // Start new conversion}

Timer_a isr

#pragma vector=TIMERA1_VECTOR __interrupt void TimerA_ISR (void){ ADC12CTL0&= ~ADC12SC; //start new conversion TACTL&= ~TAIFG; }

Analysis of operation

This laboratory uses the previous modules to construct an analogue signal chain as shown in Figure 1.

Analogue signal chain structure.

The input voltage V IN is in the range 0 V and 2.5 V, with a resolution of:

ΔV IN = ( 2.5 x V REF ) / 2 12 = 0.6 mV

The V IN value is controlled by the value in the DAC12_0DATA register.

The output voltage V o has the same characteristics as the input voltage, but scaled by a multiplication factor (gain), attributed by the OA. The OA gain is selectable through the OAFBR field in the OA0CTL1 register.

The V o conversion result is stored in the ADC12MEM0 register.

Once the signal chain modules are configured in accordance with the previous steps, initiate the experiment by completing the file, compiling it and running it on the Experimenter’s board. For the evaluation of the peripherals discussed during this laboratory, set a breakpoint on the ADC12_ISR and perform the following operations:

- Configure the DAC12_0DATA register with the value 0xFF. With the aid of a voltmeter, measure the analogue input voltage A6 (DAC12 channel 0 output). The value should be in the region of 0.15 V;

- Measure the input voltage A1 (OA0’s output). The voltage value should be the same;

- Execute the code. Verify the ADC12’s conversion result. The value should be similar to the one of the DAC12_0DATA register;

- Double the amplifier gain (2x). Verify the voltage at A0. It should be the double of the input voltage A1 (OA0’s output) given in step 2;

- Execute the code. Verify the ADC12’s conversion result. The value should be two times the value of the DAC12_0DATA register;

- Execute further modifications in order to evaluate the digital-to-analogue and analogue-to-digital conversion. Do not exceed the Vo maximum value (2.5 V).

This example and many others are available on the MSP430 Teaching ROM.

Request this ROM, and our other Teaching Materials here (External Link)

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Source:  OpenStax, Teaching and classroom laboratories based on the “ez430” and "experimenter's board" msp430 microcontroller platforms and code composer essentials. OpenStax CNX. May 19, 2009 Download for free at http://cnx.org/content/col10706/1.3
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