In Table 7.7.8.1 we give the scaled down dimensions of MOSFET over the last 4 decades.
Table 7.7.8.1.Dimension Scaling in MOSFET over the last 4 decades.
| Year | 1967 | 1997 | 1999 | 2001 | 2003 | 2006 |
| L(μm) | 10 | 0.25 | 0.18 | 0.13 | 0.1 | 0.07 |
| DRAM(Gbit/cm 2 ) | 64M | 0.18 | 0.38 | 0.42 | 0.91 | 1.85 |
| Jn.Depth(xj nm) | 1000 | 100 | 70 | 60 | 52 | 40 |
| Interconnection Pitch(nm) | 2000 | 600 | 500 | 350 | 245 | 130 |
In Table 7.7.8.2. we give the scaling in terms of Half-Pitch and Node.
Table 7.7.8.2. Evolution of Nodes and Half-Pitch with advancing Generations.
| Year | Node(nm) | Half-Pitch(nm) | Gate Length*(nm) |
| 2009 a | 32 | 52 | 29 |
| 2007 a | 45 | 68 | ? |
| 2005 b | 65 | 90 | 32 |
| 2004 b | 90 | 90 | 37 |
| 2003 b | 100 | 100 | 45 |
| 2001 c | 130 | 150 | 65 |
| 1999 c | 180 | 230 | 140 |
| 1997 d | 250 | 250 | 200 |
| 1995 d | 350 | 350 | 350 |
| 1992 d | 500 | 500 | 500 |
a-ITRS data 2008 update.
a-ITRS data 2006
a-ITRS data 2001
a-ITRS data 1997
*The physical length has become smaller than the printed length.
7.7.9.Limits due to Interconnection.
In Figure 7.7.9.1 we have defined the width(W), thickness(t) and spacing (S) of the metal pathway/metal interconnection at the same level and height (h)of the oxide layer separating two adjacent level metal pathways.
We have two scaling models. One model is fixed thiockness and the other is scaled thickness.
Wire length will be short for ‘local innterconects’ and will be chip long for ‘global interconnects’.
Die size will be scaled by D C = 1.1. As we scale down, the die size is scaled up so as to build more and more complex ‘System-on-Chip’.
In Table 7.7.9.1 we give the performance of local and global interconnects.
Table 7.7.9.1. Influence of Scaling on Interconnect Characteristics.
| Parameter | ___________ | Var.’t’ | Const.’t’ |
| Width(W) | 1/S | 1/S | |
| Spacing(S) | 1/S | 1/S | |
| Thickness(t) | 1/S | 1 | |
| Interlayer Oxide height(h) | 1/S | 1/S | |
| Characteristics per unit length | |||
| Wire Resistance per unit length | R W =1/(Wt) | S 2 | S |
| Fringing Cap.per unit length | C Wf =t/S | 1 | S |
| Parallel Plate Cap.per unit length | C Wp =W/h | 1 | 1 |
| Total Wire Cap per unit length | C W = C Wf + C Wp | 1 | 1 to S |
| Unrepeated RC per unit length | t WU = R W C W | S 2 | S to S 2 |
| Repeated RC per unit length* | t WR =√(RC R W C W ) | √S | 1 to √S |
| Cross Talk (Noise) | t/S | 1 | S |
| Local/scaled Interconnect Delay | |||
| Length(L) | L | 1/S | 1/S |
| Unrepeated Wire RC delay | L 2 t WU | 1 | 1/S to 1 |
| Repeated Wire RC delay | Lt WR | 1/√S | 1/S to 1/√S |
| Global Interconnect Delay | |||
| Length(Chip length) | L | D C | D C |
| Unrepeated Wire RC delay | L 2 t WU | S 2 D C 2 | SD C 2 to S 2 D C 2 |
| Repeated Wire RC delay | Lt WR | D C √S | D C to D C √S |
*Asuming constant field scaling of gates.
7.7.9.1.Interconnect Delays are limiting the performance with advanced Generations of Technology
Inspection of Table 7.7.9.1 leads us to the following conclusions
- Wire Capacitances per micron is remaining constant at 0.2femto Farads/μm. This is roughly 1/10 of gate capacitance;
- Local wires are getting faster but not quite as fast as the Gates but that is not a major problem.
- Global wires are getting slower.
In Figure 7.7.9.1 we make a comparative study of the Gate Delays, Interconnect delays and the overall delay. We clearly see a minimum dealy of 12 psec at Node 250nm for Al and SiO 2 and a minimum delay of 8 psec at Node 180nm for Cu and low-K interconnect. This is the reason why IBM has completely switched over to Copper and low-K interconnects.
7.7.9.2.Ways and means for overcoming the Interconnect Bottleneck of cost and performance.